Package with integrated inductor and/or capacitor

• US 6,744,114 B2
• Filed: 08/28/2002
• Issued: 06/01/2004
• Est. Priority Date: 08/29/2001
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Dentry, James F., Peczalski, Andrezej
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/232,269
• Publication Number:
  US 20030045044A1
• Time in Patent Office: 643 Days
• Field of Search: 438/106, 438/113, 438/127, 438/612, 365/129
• US Class Current: 257/532
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2223/6672 for integrated passive components, e.g. semiconductor device with passive components only
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Methods for attaching two wafers are presented along with devices resulting from such methods. In one illustrative embodiment, a first wafer is provided having pillars for conducting an electric signal. The wafer also includes an electronic device such as an inductor or capacitor that may in some instances consume relatively large amounts of space. The first wafer is bonded to a second wafer so that a circuit on the second wafer may be electrically connected to the electronic device of the first wafer.

Claims

1. A device comprising:

a first wafer having a first side and a second side, the first wafer including an electronic component and an electrically conductive element;

a second wafer having a first side and a second side, the first side of the second wafer including at least one pit having a bottom wall and at least one perimeter wall, the pit defining at least one pillar where the pillar is spaced from at least one perimeter wall of the pit, at least part of the pillar being adapted to be electrically conductive, wherein the second wafer includes an electronic device that is electrically coupled to the at least part of the pillar that is electrically conductive;

wherein the first wafer is attached to the second wafer such that the at least part of the pillar that is electrically conductive is electrically coupled to the electrically conductive element.

2. The device of claim 1 wherein the at least part of the pillar that is adapted to be electrically conductive includes a metallization layer over a portion of the pillar.

3. The device of claim 1 wherein the at least part of the pillar that is adapted to be electrically conductive includes a doped region of the pillar.

4. The device of claim 1 wherein the electronic device is disposed adjacent to the second side of the second wafer.

5. The device of claim 1 wherein the electronic device is disposed adjacent to the bottom wall of the pit of the second wafer.

6. The device of claim 1 wherein the electronic device is integral to the second wafer.

7. The device of claim 1 wherein the electronic device is an inductor.

8. The device of claim 1 wherein the electronic device is a capacitor.

9. The device of claim 1 wherein the electronic device is a transistor.

10. The device of claim 1 wherein the at least part of the pillar that is adapted to be electrically conductive provides an electronic connection between the electronic device and the electrically conductive element.

11. A device as in claim 1 wherein the first wafer is attached to the first side of the second wafer such that the pit forms part of a cavity defined between the first wafer and the second wafer.

12. A device as in claim 11 wherein the electronic device is positioned within the cavity.

13. A device as in claim 1 wherein the at least part of the pillar that is electrically conductive is electrically coupled to the electrically conductive element by an electrical connection that is entirely between the first wafer and the second wafer.

14. A device comprising:

a first wafer including a pit formed in a surface of the first wafer, the pit having at least one perimeter wall, and the pit forming a pillar wherein the pillar is spaced from at least one perimeter wall of the pit, the first wafer also having a first electronic device incorporated into or attached to the first wafer;

a second wafer having a second electronic device, the second wafer bonded to the first wafer;

means for conducting an electronic signal from the first electronic device to the second electronic device, the means for conducting engaged and traveling along at least part of the pillar.

15. A device comprising:

a wafer having a first side and a second side, the first side having an area removed to form a pit having at least one perimeter wall, the pit defining a pillar wherein at least part of the pillar is spaced from at least one perimeter wall of the pit;

a first electrically conductive means engaging a first region of the pillar;

a second electrically conductive means engaging a second region of the pillar, wherein there is a discontinuity between the first region and the second region; and

an electronic device engaged with the wafer, the electronic device having a first lead electrically coupled to the first electrically conductive means and a second lead electrically coupled to the second electrically conductive means.

16. The device of claim 15 wherein the electronic device is engaged with the second side of the wafer.

17. The device of claim 15 wherein the electronic device is provided within the pit.

18. The device of claim 15 wherein the electronic device is an inductor formed by deposition of metal within the pit.

19. The device of claim 15 wherein the electronic device includes a capacitor, the capacitor including:

a first layer of metal electrically coupled to the first conductive means;

a second layer of metal electrically coupled to the second conductive means; and

a dielectric separating the first layer of metal from the second layer of metal.

20. A device comprising:

a wafer having a first side and a second side with an area of the first side removed to form a pit having at least one perimeter wall, the pit defining a first pillar and a second pillar, wherein at least part of the first pillar and/or second pillar is spaced from at least one perimeter wall of the pit;

first electrically conductive means engaged with a region of the first pillar;

second electrically conductive means engaged with a region of the second pillar; and

metal deposited within the pit, the metal formed to define a first portion and a second portion, the first portion and second portion electrically isolated from one another by a layer of dielectric; and

wherein the first portion is electrically coupled to the first electrically conductive means and the second portion is electrically coupled to the second electrically conductive means, the metal and the dielectric adapted to form a capacitor.

21. The device of claim 20 wherein the metal is formed such that the first portion and the second portion define an interleaving comb structure defining a channel therebetween, the channel including at least some of the dielectric.

22. The device of claim 20 wherein the capacitor formed by the metal and the dielectric is fabricated and then placed within the pit.

23. The device of claim 20 wherein the metal and the dielectric are assembled within the pit to form the capacitor.

24. A device comprising:

a first wafer with a pit defining at least one pillar, at least part of the pillar being electrically conductive; and

a second wafer having at least one conductive region;

wherein the first wafer is bonded to the second wafer such that the conductive region of the second wafer is in electrical contact with the electrically conductive portion of the pillar and the pit defines a cavity between the first wafer and the second wafer with the pillar therein.

25. The device of claim 24 wherein the cavity is a hermetically sealed cavity.