Method for phase locking in a phase lock loop

• US 6,744,323 B1
• Filed: 08/30/2001
• Issued: 06/01/2004
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Moyal, Nathan Y., Gehring, Mark R., Moen, Russell, Ragan, Lawrence
• Primary Examiner(s): Tokar, Michael J.
• Assistant Examiner(s): Nguyen, Linh V
• Application Number:
  US09/943,149
• Time in Patent Office: 1,006 Days
• Field of Search: 331/DIG.2, 331/1.A, 331/16, 331/18, 331/78, 331/34, 331/25, 375/374, 375/376, 327/156, 327/158, 327/147, 327/149
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

An apparatus comprising a phase lock loop (PLL) and a lock circuit. The PLL may be configured to multiply an input frequency in response to a lock signal. The lock circuit may be configured to generate the lock signal. The PLL may also be configured to select a reference frequency as (i) the input frequency when in a first mode and (ii) a divided frequency of the input frequency when in a second mode.

Claims

1. An apparatus comprising:

a phase lock loop (PLL) configured to multiply an input frequency to generate an output frequency in response to a multi-bit lock signal; and

a lock circuit configured to generate said multi-bit lock signal, wherein said PLL is configured to (i) (a) select a reference frequency as said input frequency and (b) select a first feedback ratio, when in a first mode and (ii) (a) select one of a plurality of divided frequencies of said reference frequency to be said input frequency and (b) select a second feedback ratio, when in a second mode, wherein (i) said selected divided frequency is selected in response to said multi-bit lock signal, (ii) a first bit of said multi-bit lock signal selects said first feedback ratio, and (iii) a second bit of said multi-bit lock signal selects said second feedback ratio.

2. The apparatus according to claim 1, wherein said first mode is further configured to increase said first feedback ratio.

3. The apparatus according to claim 2, wherein said second mode is further configured to decrease said second feedback ratio.

4. The apparatus according to claim 1, wherein said lock circuit comprises a lock decision logic circuit.

5. The apparatus according to claim 1, wherein said lock circuit comprises a timer circuit.

6. The apparatus according to claim 1, wherein said lock signal is generated in further response to an internal/external signal.

7. The apparatus according to claim 1, wherein said lock is controlled by a timer.

8. The apparatus according to claim 1, wherein said multi-bit lock is externally controlled by a user.

9. The apparatus according to claim 1, wherein said PLL comprises:

a first switchable divider configured to generate a reference frequency in response to said input frequency;

a PLL logic circuit configured to generate said output frequency in response to said reference frequency and a feedback frequency; and

a second switchable divider configured to generate said feedback frequency in response to said output frequency.

10. The apparatus according to claim 9, wherein said first and second switchable dividers are further configured in response to said multi-bit lock signal.

11. The apparatus according to claim 10, wherein:

said first switchable divider comprises a first divider and a first multiplexer, wherein said first multiplexer is configured to select a first divided output frequency or said input frequency as said reference frequency; and

said second switchable divider comprises a second divider, a third divider and a second multiplexer, wherein said multiplexer is configured to select a second divided output frequency or a third divided frequency as said feedback frequency.

12. The apparatus according to claim 11, wherein said second and third dividers are configured in series.

13. The apparatus according to claim 11, wherein said second and third dividers are configured in parallel.

14. The apparatus according to claim 11, wherein said second and third dividers comprise multi-channel dividers configured in response to said multi-bit lock signal.

15. An apparatus comprising:

means for multiplying an input frequency in response to a lock signal;

means for generating an output frequency in response to said input frequency;

means for generating said lock signal; and

means for (i) (a) selecting a reference frequency to be said input frequency and (b) selecting a first feedback ratio, when in a first mode and (ii) (a) selecting one of a plurality of divided frequencies of said reference frequency to be said input frequency and (b) selecting a second feedback ratio, when in a second mode, wherein (i) said selected divided frequency is selected in response to said multi-bit lock signal, (ii) a first bit of said multi-bit lock signal selects said first feedback ratio, and (iii) a second bit of said multi-bit lock signal selects said second feedback ratio.

16. A method for frequency and/or phase acquisition in a phase lock loop (PLL), comprising the steps of:

(A) multiplying an input frequency in response to a lock signal;

(B) generating said lock signal; and

(C) (i) (a) selecting said reference frequency to be said input frequency and (b) selecting a first feedback ratio, when in a first mode and (ii) (a) selecting one of a plurality of divided frequencies of said reference frequency to be said input frequency and (b) selecting a second feedback ratio, when in a second mode, wherein (i) said selected divided frequency is selected in response to said multi-bit lock signal, (ii) a first bit of said multi-bit lock signal selects said first feedback ratio, and (iii) a second bit of said multi-bit lock signal selects said second feedback ratio.

17. The method according to claim 16, wherein step (A) further comprises:

increasing said first feedback ratio when in said first mode; and

decreasing said second feedback ratio when in said second mode.

18. The method according to claim 16, wherein step (B) generates said lock signal in further response to an internal/external signal.

19. The method according to claim 16, wherein step (A) further comprises:

generating a reference frequency in response to said input frequency;

generating an output frequency in response to said reference frequency and a feedback frequency; and

generating said feedback frequency in response to said output frequency.

20. The method according to claim 16, wherein step (A) further comprises:

selecting a first divided output frequency or said input frequency and presenting said reference frequency; and

selecting a second divided output frequency or a third divided frequency and presenting said feedback frequency.

21. An apparatus comprising:

a phase lock loop (PLL) configured to multiply an input frequency to generate an output frequency in response to a lock signal; and

a lock circuit configured to generate said lock signal in response to an external input derived independently from said PLL, wherein said PLL is configured to (i) select a reference frequency as said input frequency when in a first mode and (ii) select a divided frequency of said reference frequency as said input frequency when in a second mode, wherein either said first mode or said second mode is selected in response to said lock signal.