Graphics display system with video synchronization feature

• US 6,744,472 B1
• Filed: 11/09/1999
• Issued: 06/01/2004
• Est. Priority Date: 11/09/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A., Patterson, James T., Xie, Xiaodong
• Primary Examiner(s): Lee, Michael H.
• Assistant Examiner(s): NATNAEL, PAULOS M
• Application Number:
  US09/437,207
• Time in Patent Office: 1,666 Days
• Field of Search: 348/500, 348/513, 348/512, 348/536, 348/537, 348/538, 348/539, 348/543, 348/549, 348/553, 348/555, 348/441, 348/639, 348/505, 348/510, 348/497, 348/498, 348/450, 341/61, 345/600, 345/605
• US Class Current: 348/441
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples. The time base corrector receives samples at the output of the line-locked sample rate converter and provides samples synchronized to the display clock for reducing undesirable artifacts such as jitter.

Claims

1. A video synchronizing mechanism comprising:

a first sample rate converter for converting a sampling rate of a stream of video samples from a first sample rate to a first converted rate, said first sample rate converter comprising;

a chroma tracker capable of tracking phase and frequency of chroma bursts, comparing them against a predetermined pattern and generating an error signal based on the result of the comparison; and

a low pass filter for receiving and filtering the error signal from the chroma tracker to generate an adjustment value, wherein the adjustment value is used to adjust the first sample rate or a first down-sampling ratio, which is a ratio between the first sample rate and the first converted rate;

a filter for processing at least some of the video samples having the first converted rate; and

a second sample rate converter for converting the sampling rate from the first converted rate to a second converted rate.

2. The video synchronizing mechanism of claim 1 wherein an output of the second sample rate converter is stored in memory such that an output of the memory can be running at a display clock rate that may differ from the second converted rate.

3. The video synchronizing mechanism of claim 1 further comprising a time base corrector for synchronizing an output of the second sample rate converter to a display clock, wherein the display clock runs at a display clock rate that differs from the second converted rate.

4. The video synchronizing mechanism of claim 1 further comprising an analog-to-digital converter (ADC) for providing the stream of video samples to the first sample rate converter.

5. The video synchronizing mechanism of claim 4 wherein the ADC generates the stream of video samples with the first sample rate that is arbitrary.

6. The video synchronizing mechanism of claim 5 wherein the first sample rate is greater than four times the chroma sub-carrier frequency.

7. The video synchronizing mechanism of claim 1 wherein the first sample rate is fixed, and the stream of video samples is generated using a free-running input sample clock.

8. The video synchronizing mechanism of claim 7 wherein the first sample rate converter comprises a sample rate converter for down-sampling the stream of video samples using the first down-sampling ratio.

9. The video synchronizing mechanism of claim 1 wherein the first sample rate is variable, and the adjustment value is used to adjust the first sample rate.

10. The video synchronizing mechanism of claim 9 wherein the first sample rate converter comprises a sample rate converter for down-sampling the stream of video samples using the first down-sampling ratio.

11. The video synchronizing mechanism of claim 1 wherein the filter for processing at least some of the video samples having the first converted rate includes a comb filter for performing a luma/chroma separation.

12. The video synchronizing mechanism of claim 11 wherein the comb filter is an adaptive 2 H comb filter.

13. The video synchronizing mechanism of claim 1 wherein the second sample rate converter comprises a sample rate converter module for down-sampling the video samples having the first converted rate.

14. The video synchronizing mechanism of claim 1 wherein the first sample rate is fixed, and the stream of video samples is generated using an input sample clock, which is line locked to an analog video input.

15. The video synchronizing mechanism of claim 14 wherein the first sample rate converter converts the sampling rate of the stream of video samples from the first sample rate to the first converted rate, which is equal to four times the chroma sub-carrier frequency.

16. The video synchronizing mechanism of claim 15 further comprising a comb filter, and the comb filter is used to perform a luma/chroma separation of the samples having the first converted rate into demodulated luma and chroma component video signals.

17. The video synchronizing mechanism of claim 16 wherein the second sample rate converter down-samples the demodulated luma and chroma component video signals to have the second converted rate.

18. The video synchronizing mechanism of claim 17 wherein the second converted rate is 13.5 MHz.

19. A video synchronizing mechanism comprising:

a first sample rate converter for converting a sampling rate of a stream of video samples from a first sample rate to a first converted rate;

a filter for processing at least some of the video samples having the first converted rate; and

a second sample rate converter for converting the sampling rate from the first converted rate to a second converted rate,

wherein the first sample rate of the stream of video samples is fixed, and the stream of video samples is generated using a free-running input sample clock, and

wherein the first sample rate converter comprises a sample rate converter for down-sampling the stream of video samples, and a chroma tracker for tracking phase and frequency of chroma bursts and comparing them against an expected pattern, and the chroma tracker generates an error signal based on the result of the comparison, and

wherein the first sample rate converter further comprises a low pass filter for filtering the error signal of the chroma tracker and providing a first adjustment value to the sample rate converter to adjust a first down-sampling ratio, which is a ratio between the first sample rate and the first converted rate.

20. The video synchronizing mechanism of claim 19, wherein the first down-sampling ratio is 35/(66+epsilon), where epsilon is the first adjustment value.

21. The video synchronizing mechanism of claim 20 wherein the first sample rate is 27 MHz.

22. The video synchronizing mechanism of claim 21 wherein the first converted rate is equal to four times the chroma sub-carrier frequency.

23. The video synchronizing mechanism of claim 22 wherein the four times the chroma sub-carrier frequency is about 14.318 MHz.

24. The video synchronizing mechanism of claim 22 wherein the four times the chroma sub-carrier frequency is about 17.72 MHz.

25. A video synchronizing mechanism comprising:

a first sample rate converter for converting a sampling rate of a stream of video samples from a first sample rate to a first converted rate;

a filter for processing at least some of the video samples having the first converted rate; and

a second sample rate converter for converting the sampling rate from the first converted rate to a second converted rate,

wherein the first sample rate of the stream of video samples is variable, and

wherein the first sample rate converter comprises;

a sample rate converter for down-sampling the stream of video samples,

a chroma tracker for tracking phase and frequency of chroma bursts and comparing them against an expected pattern, wherein the chroma tracker generates an error signal based on the result of the comparison, and

a low pass filter for filtering the error signal of the chroma tracker and generates an output, which is used to adjust the first sample rate.

26. A video synchronizing mechanism comprising:

a first sample rate converter for converting a sampling rate of a stream of video samples from a first sample rate to a first converted rate;

a filter for processing at least some of the video samples having the first converted rate; and

a second sample rate converter for converting the sampling rate from the first converted rate to a second converted rate,

wherein the first sample rate of the stream of video samples is variable, and

wherein the first sample rate converter comprises a sample rate converter for down-sampling the stream of video samples, and a chroma tracker for tracking phase and frequency of chroma bursts and comparing them against an expected pattern, wherein the chroma tracker generates an error signal based on the result of the comparison, and

wherein the first sample rate converter further comprises a low pass filter for filtering the error signal of the chroma tracker and generates an output, and

wherein the first sample rate converter further comprises a voltage controlled oscillator, wherein the first sample rate is an oscillation frequency of the voltage controlled oscillator, and the voltage controlled oscillator receives the output of the low pass filter and uses it to adjust the oscillating frequency.

27. The video synchronizing mechanism of claim 26 wherein a first down-sampling ratio of the sample rate converter is fixed at 35/66.

28. The video synchronizing mechanism of claim 27 wherein the first converted rate is equal to four times the chroma sub-carrier frequency.

29. The video synchronizing mechanism of claim 28 wherein the four times the chroma sub-carrier frequency is about 14.318 MHz.

30. The video synchronizing mechanism of claim 28 wherein the four times the chroma sub-carrier frequency is about 17.72 MHz.

31. A video synchronizing mechanism comprising:

a first sample rate converter for converting a sampling rate of a stream of video samples to a first converted rate;

a filter for processing at least some of the video samples having the first converted rate; and

a second sample rate converter for converting the sampling rate from the first converted rate to a second converted rate,

wherein the second sample rate converter comprises a sample rate converter module for down-sampling the video samples having the first converted rate, and

a horizontal sync tracker for detecting horizontal syncs and counting the number of samples between the horizontal syncs to a sub-sample accuracy, and the horizontal sync tracker provides a second adjustment value to the sample rate converter module to adjust a second down-sampling ratio, which is the ratio between the first converted rate and the second converted rate.

32. The video synchronizing mechanism of claim 31 wherein the second sample rate converter further comprises a YUV scaler for scaling Y, U and V components to the proper amplitudes required by ITU-R BT.601.

33. The video synchronizing mechanism of claim 31 wherein the second converted rate is nominally equal to the frequency of a display clock, but the second converted rate is locked to a multiple of a horizontal line rate of the video samples having the first converted rate, and not to the display clock.

34. The video synchronizing mechanism of claim 33 wherein the second converted rate is locked to 858 times the horizontal line rate of the video samples having the first converted rate.

35. The video synchronizing mechanism of claim 33 wherein the second converted rate is locked to 864 times the horizontal line rate of the video samples having the first converted rate.

36. The video synchronizing mechanism of claim 31 wherein the horizontal sync tracker counts the number of samples between two adjacent horizontal syncs to a sub-sample accuracy.

37. The video synchronizing mechanism of claim 36 wherein the horizontal sync tracker counts the number of samples between two adjacent horizontal syncs to an accuracy of {fraction (1/16)}^th of a sample period.

38. The video synchronizing mechanism of claim 36 wherein leading edges of the horizontal syncs are measured to a sub-sample accuracy.

39. The video synchronizing mechanism of claim 38 wherein the number of samples with the first converted rate is counted between two adjacent horizontal syncs.

40. The video synchronizing mechanism of claim 39 wherein the number of samples with the first converted rate between the two adjacent horizontal syncs include the number of fractional samples derived from measuring the leading edges of the horizontal syncs to the sub-sample accuracy.

41. The video synchronizing mechanism of claim 38 wherein the leading edges of the horizontal syncs are measured to a sub-sample accuracy by using interpolation.

42. The video synchronizing mechanism of claim 31 wherein the sample rate converter module interpolates the samples by 33 and decimates by 35+(the second adjustment value).

43. The video synchronizing mechanism of claim 31 wherein the second sample rate converter further comprises a low pass filter, and the low pass filter receives the second adjustment value from the horizontal sync tracker, filters the second adjustment value, and provides the filtered second adjustment value to the sample rate converter module.

44. A method of synchronizing video comprising the steps of:

converting a sampling rate of a stream of video samples from a first sample rate to a first converted rate, comprising;

tracking phase and frequency of chroma bursts;

comparing said phase and frequency against a predetermined pattern;

generating an error signal based on the result of the comparison;

filtering the error signal to generate an adjustment value; and

adjusting, using the adjustment value, the first sample rate or a first down-sampling ratio, which is a ratio between the first sample rate and the first converted rate;

processing at least some of the video samples having the first converted rate; and

converting the sampling rate from the first converted rate to a second converted rate.

45. The method of synchronizing video of claim 44 further comprising the step of converting an input video signals from analog video signals to digital video signals, wherein the digital video signals are generated using an input sample clock.

46. The method of synchronizing video of claim 45 wherein the input sample clock is free-running.

47. The method of synchronizing video of claim 45 wherein the input sample clock is line locked to the input video signals.

48. The method of synchronizing video of claim 46 wherein the input sample clock has a fixed frequency.

49. The method of synchronizing video of claim 48 wherein the frequency of the input sample clock is fixed at 27 MHz.

50. The method of synchronizing video of claim 46 wherein the frequency of the input sample clock is variable.

51. The method of synchronizing video of claim 44 wherein the first converted rate is four times the chroma sub-carrier frequency.

52. The method of synchronizing video of claim 44 wherein the step of processing at least some of the video samples having the first converted rate comprises the step of performing a luma/chroma separation.

53. The method of synchronizing video of claim 52 wherein the luma/chroma separation is performed using a comb filter.

54. The method of synchronizing video of claim 44 further comprising the steps of storing the output of the second sample rate converter in a FIFO, and start outputting the stored output of the second sample rate converter from memory when the FIFO is about half full.

55. A method of synchronizing video comprising the steps of:

converting a sampling rate of a stream of video samples from a first sample rate to a first converted rate;

processing at least some of the video samples having the first converted rate; and

converting the sampling rate from the first converted rate to a second converted rate,

wherein the step of converting the sampling rate of the stream of video samples from the first sample rate to the first converted rate comprises the steps of tracking phase and frequency of chroma bursts, comparing them against an expected pattern, generating an error signal based on the result of the comparison, low pass filtering the error signal, and providing the filtered error signal as a first adjustment value to a sample rate converter to adjust a first down-sampling ratio, which is the ratio between the first sample rate and the first converted rate.

56. A method of synchronizing video comprising the steps of:

converting a sampling rate of a stream of video samples from a first sample rate to a first converted rate;

processing at least some of the video samples having the first converted rate; and

converting the first converted rate to a second converted rate,

wherein the step of converting the sampling rate of the stream of video samples from the first sample rate to the first converted rate comprises the steps of tracking phase and frequency of chroma bursts, comparing them against an expected pattern, and generating an error signal based on the result of the comparison, low pass filtering the error signal, and providing the filtered error signal to a voltage controlled oscillator to adjust the first sample rate.

57. A method of synchronizing video comprising the steps of:

converting a sampling rate of a stream of video samples to a first converted rate;

processing at least some of the video samples having the first converted rate; and

converting the sampling rate from the first converted rate to a second converted rate,

wherein the step of converting the first converted rate to the second converted rate comprises the steps of detecting horizontal syncs to a sub-sample accuracy, counting the number of samples between the horizontal syncs, generating a second adjustment value, and using the second adjustment value to adjust a second down-sampling ratio, which is a ratio between the first converted rate and the second converted rate.

58. The method of synchronizing video of claim 57 wherein the step of converting the first converted rate to the second converted rate further comprises the step of low pass filtering the second adjustment value prior to using the second adjustment value to adjust the second down-sampling ratio.

59. A video synchronizing mechanism comprising:

a first sample rate converter for converting a sampling rate of a stream of video samples to a first converted rate, the first sample rate converter comprising;

a chroma tracker for tracking phase and frequency of chroma bursts, comparing them against a predetermined pattern and generating an error signal based on the result of the comparision; and

a low pass filter for receiving and filtering the error signal from the chroma tracker to generate an adjustment value, wherein the adjustment value is used to adjust the first sample rate or a first down-sampling ratio, which is a ratio between the first sample rate and the first converted rate;

a filter for processing at least some of the video samples having the first converted rate;

a second sample rate converter for converting the sampling rate from the first converted rate to a second converted rate; and

a time base corrector for synchronizing the output of the second sample rate converter to a display clock, wherein the display clock runs at a display clock rate that differs from the second converted rate,

wherein the time base corrector comprises a FIFO for receiving an output of the second sample rate converter as an input and providing an output that is synchronous to the display clock.

60. The video synchronizing mechanism of claim 59 wherein the time base corrector further comprises a time base corrector controller for controlling the FIFO to convert the input with the second converted rate to the output that is synchronous to the display clock.

61. The video synchronizing mechanism of claim 60 wherein the time based corrector controller delays vertical syncs from the input by time to fill about half the FIFO with the input.

62. The video synchronizing mechanism of claim 61 wherein the time based corrector controller generates timing signals synchronously to the delayed vertical syncs, and the timing signals include horizontal syncs.

63. The video synchronizing mechanism of claim 59 wherein the FIFO is filled with the input to approximately one half of its size prior to starting to provide the output.

64. The video synchronizing mechanism of claim 59 wherein the FIFO has a size of a horizontal line.

65. The video synchronizing mechanism of claim 59 wherein the FIFO has a size larger than a horizontal line.

66. The video synchronizing mechanism of claim 59 wherein the FIFO has a size smaller than a horizontal line.

67. The video synchronizing mechanism of claim 59 wherein the FIFO is filled with the input to more than half of its size prior to starting providing the output.

68. The video synchronizing mechanism of claim 59 wherein the FIFO is filled with the input to less than half of its size prior to starting providing the output.