Data pipeline timing optimization technique in a multi-port bridge for a local area network

• US 6,744,728 B1
• Filed: 03/19/1999
• Issued: 06/01/2004
• Est. Priority Date: 09/17/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: SONY CORPORATION & SONY ELECTRONICS, INC.
• Inventors: Chung, David
• Primary Examiner(s): Nguyen, Chau
• Assistant Examiner(s): HYUN, SOON D
• Application Number:
  US09/273,134
• Time in Patent Office: 1,901 Days
• Field of Search: 370/229, 370/230-235, 370/389, 370/392, 370/400, 370/401
• US Class Current: 370/229
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 12/462 LAN interconnection over a bridge based backbone
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/135 by jamming the transmission media
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout

Abstract

A method of optimizing a data path in a multi-port bridge for a local area network (LAN) includes steps of: identifying a data path through the multi-port bridge wherein the data path includes a plurality of stages in a serial arrangement, wherein each stage performs a corresponding operation on data received from the LAN by the multi-port bridge; identifying a stage in the data path wherein the identified stage requires a period of time to perform its corresponding operation which is longer than any other stage; and subdividing the identified stage into two or more subdivided stages wherein the operations performed by the subdivided stages collectively perform the operation associated with the identified stage and wherein each of the two or more subdivided stages requires a period of time to perform its corresponding operation which is shorter than the period of time required for the identified stage to perform its corresponding operation. The method can include determining a bandwidth required for the multi-port bridge; and determining a frequency for a clock signal based upon the bandwidth. The method can also include repeatedly subdividing selected stages until a slowest stage in the data path is operable according to the clock signal. The invention results in a beneficial trade-off in which bandwidth for the multi-port bridge and latency are both increased.

Claims

1. A method of optimizing a data path in a multi-port bridge for a local area network (LAN) comprising a plurality of segments, wherein the method comprises:

a. identifying a data path through the multi-port bridge wherein the data path includes a plurality of stages arranged in serial, wherein each stage performs a corresponding operation on data received from a sending segment of the LAN by the multi-port bridge prior to transmission of the data to a receiving segment of the LAN by the multi-port bridge, and further wherein the identified data path is a receive data path by which packets are received from the sending segment of the LAN by a port of the multi-port bridge and stored in a packet buffer included in the multi-port bridge;

b. identifying a stage in the data path wherein the identified stage requires a period of time to perform its corresponding operation which is longer than a period of time required by any other stage in the receive data path; and

c. subdividing the identified stage into two or more subdivided stages wherein each of the subdivided stages performs a corresponding operation and wherein the operations performed by the subdivided stages collectively perform the operation associated with the identified stage and wherein each of the two or more subdivided stages requires a corresponding period of time to perform its corresponding operation which is shorter than the period of time required for the identified stage to perform its corresponding operation.

2. The method according to claim 1 further comprising repeating identifying a stage and subdividing the stage.

3. A method of optimizing a data path in a multi-port bridge for a local area network (LAN) comprising a plurality of segments, wherein the method comprises:

a. identifying a data path through the multi-port bridge wherein the data path includes a plurality of stages arranged in serial, wherein each stage performs a corresponding operation on data received from a sending segment of the LAN by the multi-port bridge prior to transmission of the data to a receiving segment of the LAN by the multi-port bridge, and further wherein the identified data path is a transmit data path by which packets are retrieved from a packet buffer included in the multi-port bridge and transmitted to the receiving segment of the LAN;

b. identifying a stage in the data path wherein the identified stage requires a period of time to perform its corresponding operation which is longer than a period of time required by any other stage in the transmit data path; and

c. subdividing the identified stage into two or more subdivided stages wherein each of the subdivided stages performs a corresponding operation and wherein the operations performed by the subdivided stages collectively perform the operation associated with the identified stage and wherein each of the two or more subdivided stages requires a corresponding period of time to perform its corresponding operation which is shorter than the period of time required for the identified stage to perform its corresponding operation.

4. The method according to claim 3 further comprising repeating identifying a stage and subdividing the stage.

5. A method of optimizing a data path in a multi-port bridge for a local area network (LAN) comprising a plurality of segments, wherein the method comprises:

a. identifying a data path through the multi-port bridge wherein the data path includes a plurality of stages arranged in serial, wherein each stage performs a corresponding operation on data received from a sending segment of the LAN by the multi-port bridge prior to transmission of the data to a receiving segment of the LAN by the multi-port bridge;

b. identifying a stage in the data path wherein the identified stage requires a period of time to perform its corresponding operation which is longer than any other stage in the data path; and

c. subdividing the identified stage into two or more subdivided stages wherein each of the subdivided stages performs a corresponding operation and wherein the operations performed by the subdivided stages collectively perform the operation associated with the identified stage and wherein each of the two or more subdivided stages requires a corresponding period of time to perform its corresponding operation which is shorter than the period of time required for the identified stage to perform its corresponding operation.

6. The method according to claim 5 further comprising:

a. determining a bandwidth for the multi-port bridge by summing a throughput capacity of each of a plurality of ports of the multi-port bridge; and

b. determining a frequency for a clock signal based upon the bandwidth and a width of the data bus wherein data traverses the data bus according to the clock signal.

7. The method according to claim 6 further comprising repeating identifying a stage and subdividing the stage until a slowest stage in the data path is operable according to the clock signal.

8. The method according to claim 7 further comprising applying the clock signal to the serial data path wherein data progresses through the serial data path according to the clock signal.