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Filter system and method to suppress interference imposed upon a frequency-division multiplexed channel

  • US 6,744,883 B1
  • Filed: 01/07/2000
  • Issued: 06/01/2004
  • Est. Priority Date: 01/12/1999
  • Status: Expired due to Fees
First Claim
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1. A filter system that suppresses interference imposed on at least one communications channel by at least one signal component outside of a specified amplitude range, the filter system comprising:

  • at least one filter stage having an amplitude-dependent transfer function, the amplitude-dependent transfer function implemented using at least one bi-directional current limiting filter, the at least one bi-directional current limiting filter comprising;

    a first terminal;

    a second terminal, the at least one bi-directional current limiting filter suppressing current outside a first specified amplitude range when the current enters the first terminal and exits the second terminal and suppressing current outside a second specified amplitude range when the current enters the second terminal and exits the first terminal;

    a first transistor having a first current carrying electrode, a second current carrying electrode, and a first control electrode activated by a first variable;

    a second transistor having a third current carrying electrode, a fourth current carrying electrode, and a second control electrode activated by a second variable, the second variable being inversely related to the first variable;

    a first diode having its anode connected to a first internal node and having its cathode connected to the first terminal;

    a second diode having its anode connected to a second internal node and having its cathode connected to the second terminal;

    the first transistor with the first control electrode, the first current carrying electrode, and the second current carrying electrode, the first control electrode being connected to a third internal node, the first current carrying electrode being connected to the first internal node, and the second current carrying electrode being connected to the first terminal;

    the second transistor with the second control electrode, the third current carrying electrode, and the fourth current carrying electrode, the second control electrode being connected to a fourth internal node, the third current carrying electrode being connected to the second internal node, and the fourth current carrying electrode being connected to the second terminal; and

    a load network connected to the first internal node, the second internal node, the third internal node, and the fourth internal node.

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