Integrated chip package structure using silicon substrate and method of manufacturing the same

• US 6,746,898 B2
• Filed: 06/17/2002
• Issued: 06/08/2004
• Est. Priority Date: 12/31/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US10/174,462
• Publication Number:
  US 20030124835A1
• Time in Patent Office: 722 Days
• Field of Search: 257/706, 257/707, 257/712, 257/713, 257/717, 257/720, 257/723, 257/700, 257/701, 257/702, 257/703, 257/758, 257/759, 438/122, 438/33, 438/68, 438/108, 438/110, 438/113, 438/114, 438/115, 438/458, 438/459, 438/460, 438/462, 438/464, 438/465, 438/622, 438/365, 438/386, 438/387, 361/704, 361/709-712
• US Class Current: 438/113
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions, to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Claims

1. A chip packaging method comprising:

providing a substrate having a heat sink and a film layer, the film layer positioned on a surface of the heat sink;

forming a plurality of openings penetrating through the film layer and exposing the surface of the heat sink;

providing a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface;

mounting the dies onto the surface of the heat sink exposed by the openings of the film layer, the backside of the dies facing the surface of the heat sink;

allocating a first dielectric layer over the film layer and the active surface of the dies, the first dielectric layer patterned to form a plurality of first thru-holes that penetrate through the first dielectric layer and expose the metal pads of the dies; and

allocating a first patterned wiring layer over the first dielectric layer, the first patterned wiring layer electrically connected to the metal pads of the dies through the first thru-holes.

2. The method of claim 1, wherein the dies perform same functions.

3. The method of claim 1, wherein the dies perform different functions.

4. The method of claim 1, wherein after allocating the first patterned wiring layer over the first dielectric layer, the method further comprises performing a singularizing process to form multiple chip package structures, each having a single die or a plurality of dies.

5. The method of claim 4, wherein before the singularizing process is performed, multiple bonding points are allocated on the first patterned wiring layer.

6. The method of claim 5, wherein the bonding points are selected from a group consisting of solder balls, bumps, and pins.

7. The method of claim 1, wherein the dies have a height substantially equal to that of the film layer.

8. The method of claim 1, wherein the material constituting the film layer comprises silicon.

9. The method of claim 1, wherein the openings of the film layer are formed by wet etching until the openings expose the heat sink.

10. The method of claim 1, wherein the heat sink comprises a metal.

11. The method of claim 1, wherein the step of allocating the first patterned wiring layer on the first dielectric layer comprises allocating a plurality of first vias by filling part of a conductive material of the first patterned conductive layer into the thru-holes to electrically connect the first patterned wiring layer and the metal pads of the dies by the first vias.

12. The method of claim 1, wherein before allocating the first patterned wiring layer on top of the firs dielectric layer, the method comprises filling the first thru-holes with a conductive material to form a plurality of first vias, by which the first patterned wiring layer and the metal pads are electrically connected.

13. The method of claim 1, wherein a material of the first dielectric layer is selected from a group consisting of polyimide, benzocyclobutene, porous dielectric material, and stress buffer material.

14. The method of claim 1, wherein the method of allocating the first patterned wiring layer on top of the first dielectric layer is selected from a group consisting of sputtering, electroplating, and electro-less plating.

15. The method of claim 1, further comprising allocating a patterned passivation layer over the first dielectric layer and the first patterned wiring layer.

16. The method of claim 1, wherein after the first patterned wiring layer are allocated, the method further comprises:

(a) allocating a second dielectric layer over the first dielectric layer and the first patterned wiring layer, the second dielectric layer patterned to form a plurality of second thru-holes that penetrate through the second dielectric layer; and

(b) allocating a second patterned wiring layer over the second dielectric layer, the second patterned wiring layer electrically connected to at least one of the dies through the second thru-holes.

17. The method of claim 16, wherein the step of allocating the second patterned wiring layer over the second dielectric layer comprises filling the second thru-holes with part of a conductive material of the second patterned wiring layer to form a plurality of second vias, by which the second patterned wiring layer is electrically connected to the first patterned wiring layer.

18. The method of claim 16, wherein before allocating the second patterned wiring layer on top of the second dielectric layer, the method comprises filling the second thru-holes with a conductive material to form a plurality of second vias, by which the second patterned wiring layer is electrically connected to the first patterned wiring layer.

19. The method of claim 16, wherein a material of the second dielectric layer is selected from a group consisting of polyimide, benzocyclobutene, porous dielectric material, and stress buffer material.

20. The method of claim 16, wherein the method of allocating the second patterned wiring layer on the second dielectric layer is selected from a group consisting of sputtering, electroplating, and electro-less plating.

21. The method of claim 16, further comprising allocating a patterned passivation layer over the second dielectric layer and the second patterned wiring layer.

22. The method of claim 16, wherein after allocating the second patterned wiring layer over the second dielectric layer, the method comprises allocating multiple bonding points over the second patterned wiring layer.

23. The method of claim 22, wherein the bonding points are selected from a group consisting of solder balls, bumps, and pins.

24. The method of claim 16, further comprising repeating step (a) and step (b) a plurality of times.

25. The method of claim 24, further comprising allocating a patterned passivation layer over the second dielectric layer and the second patterned wiring layer that is furthest away from the substrate.

26. The method of claim 16, wherein after allocating the second patterned wiring layer over the second dielectric layer, the method further comprises performing a singularizing process to form multiple chip package structures, each having a single die or a plurality of dies.

27. The method of claim 26, wherein before performing a singularizing process and after allocating the second patterned wiring layer over the second dielectric layer, the method comprises allocating multiple bonding points over the second patterned wiring layer and the bonding points are selected from a group consisting of solder balls, bumps, and pins.

28. A chip packaging method comprising:

providing a first substrate with a first surface;

providing a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface;

mounting the dies over the first surface of the first substrate, the active surfaces of the dies facing the first surface of the first substrate;

thinning the dies from the backside;

providing a second substrate with a second surface;

mounting a second substrate over the backsides of the dies, the second surface of the second substrate facing the backsides of the dies;

removing the first substrate;

allocating a first dielectric layer over the second surface of the second substrate and the active surface of the dies, the first dielectric layer patterned to form a plurality of first thru-holes that penetrate through the first dielectric layer and expose the metal pads of the dies; and

allocating a first patterned wiring layer on the first dielectric layer, the first patterned wiring layer electrically connected to the metal pads of the dies through the first thru-holes.

29. The method of claim 28, wherein the dies perform same functions.

30. The method of claim 28, wherein the dies perform different functions.

31. The method of claim 28, wherein a material of the first substrate is selected from a group consisting of glass, ceramic, silicon, and organic material.

32. The method of claim 28, wherein a material of the first filling layer is selected from a group consisting of epoxy and polymer.

33. The method of claim 28, wherein before allocating the first dielectric layer over the second surface of the silicon substrate and the active surface of the dies and after removing the substrate, the method further comprises allocating a filling layer on the second surface of the second substrate, the filling layer surrounding the peripheral of the dies and having a top surface that is coplanar to the active surface of the dies.

34. The method of claim 33, wherein a material of the second filling layer is selected from a group consisting of epoxy and polymer.

35. The method of claim 28, wherein before mounting the dies over the first surface of the first substrate, an insulating layer is allocated on the first surface of the first substrate, and during mounting the dies over the first surface of the first substrate, the dies are mounted onto the insulating layer, the active surfaces of the dies contacting the insulating layer.

36. The method of claim 35, wherein the thickness of the insulating layer is about 2 microns to 200 microns.

37. The method of claim 28, wherein the step of allocating the first patterned wiring layer on the first dielectric layer comprises filling the first thru-holes with part of a conductive material of the first patterned wiring layer to form a plurality of first vias, by which the first patterned wiring layer is electrically connected to the metal pads of the dies.

38. The method of claim 28, wherein before allocating the first patterned wiring layer on top of the first dielectric layer, the method comprises filling the first thru-holes with a conductive material to form a plurality of first vias, by which the first patterned wiring layer is electrically connected to the metal pads of the dies.

39. The method of claims 28, wherein a material of the first dielectric layer is selected from a group consisting of polyimide, benzocyclobutene, porous dielectric material, and stress buffer material.

40. The method of claim 28, wherein a method of allocating the first patterned wiring layer on the first dielectric layer is selected from a group consisting of sputtering, electroplating, and electro-less plating.

41. The method of claim 28, further comprising allocating a patterned passivation layer over the first dielectric layer and the first patterned wiring layer.

42. The method of claim 28, wherein after allocating the first patterned wiring layer on top of the first dielectric layer, multiple bonding points are allocated on the first patterned wiring layer.

43. The method of claim 42, wherein the bonding points are selected from a group consisting of solder balls, bumps, and pins.

44. The method of claim 42, wherein after allocating the bonding points on the first patterned wiring layer, the method further comprises performing a singularizing process to form multiple chip package structures, each having a single die or a plurality of dies.

45. The method of claim 28, wherein after mounting the dies over the first surface of the first substrate and before thinning the dies from the backside, the method further comprises allocating a filling layer on the first surface of the first substrate, the filling layer surrounding the dies.

46. The method of claim 28, wherein after the first patterned wiring layer are allocated, the method further comprises:

(a) allocating a second dielectric layer over the first dielectric layer and the first patterned wiring layer, the second dielectric layer patterned to form a plurality of second thru-holes that penetrate through the second dielectric layer; and

(b) allocating a second patterned wiring layer on the second dielectric layer, the second patterned wiring layer electrically connected to at least one of the dies through the second thru-holes.

47. The method of claim 46, further comprising repeating step (a) and step (b) a plurality of times.

48. The method of claim 47, further comprising allocating a patterned passivation layer on the second dielectric layer and the second patterned wiring layer that are furthest away from the second substrate.

49. The method of claim 47, wherein after the second patterned wiring layer that are furthest away from the second substrate is allocated on the second dielectric layer, multiple bonding points are allocated on the second patterned wiring layer that is furthest away from the substrate.

50. The method of claim 49, wherein the bonding points are selected from a group consisting of solder balls, bumps, and pins.

51. The method of claim 49, wherein after allocating the bonding points on the second patterned wiring layer that are furthest away from the second substrate, the method further comprises performing a singularizing process to form multiple chip package structures, each having a single die or a plurality of dies.

52. The method of claim 28, wherein a material of the second substrate is silicon.

53. The method of claim 46, wherein the step of allocating the second patterned wiring layer on the second dielectric layer comprises filling the second thru-holes with part of a conductive material of the second patterned wiring layer to form a plurality of second vias, by which the second patterned wiring layer is electrically connected to the first patterned wiring layer.

54. The method of claim 46, wherein before allocating the second patterned wiring layer on top of the second dielectric layer, the method comprises filling the second thru-holes with a conductive material to form a plurality of second vias, by which the second patterned wiring layer is electrically connected to the first patterned wiring layer.

55. The method of claim 46, wherein a material of the second dielectric layer is selected from a group consisting of polyimide, benzocyclobutene, porous dielectric material, and stress buffer material.

56. The method of claim 46, wherein a method of allocating the second patterned wiring layer on the second dielectric layer is selected from a group consisting of sputtering, electroplating, and electro-less plating.

57. The method of claim 46, further comprising allocating a patterned passivation layer over the second dielectric layer and the second patterned wiring layer.

58. The method of claim 46, wherein after allocating the second patterned wiring layer on the second dielectric layer, multiple bonding points are allocated on the second patterned wiring layer.

59. The method of claim 58, wherein the bonding points are selected from a group consisting of solder balls, bumps, and pins.

60. The method of claim 58, wherein after allocating the bonding points on the second patterned wiring layer, the method comprises performing a singularizing process to form multiple chip package structures, each having a single die or a plurality of dies.