Integrated chip package structure using silicon substrate and method of manufacturing the same
First Claim
1. A chip packaging method comprising:
- providing a substrate having a heat sink and a film layer, the film layer positioned on a surface of the heat sink;
forming a plurality of openings penetrating through the film layer and exposing the surface of the heat sink;
providing a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface;
mounting the dies onto the surface of the heat sink exposed by the openings of the film layer, the backside of the dies facing the surface of the heat sink;
allocating a first dielectric layer over the film layer and the active surface of the dies, the first dielectric layer patterned to form a plurality of first thru-holes that penetrate through the first dielectric layer and expose the metal pads of the dies; and
allocating a first patterned wiring layer over the first dielectric layer, the first patterned wiring layer electrically connected to the metal pads of the dies through the first thru-holes.
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Accused Products
Abstract
An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions, to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
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Citations
60 Claims
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1. A chip packaging method comprising:
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providing a substrate having a heat sink and a film layer, the film layer positioned on a surface of the heat sink;
forming a plurality of openings penetrating through the film layer and exposing the surface of the heat sink;
providing a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface;
mounting the dies onto the surface of the heat sink exposed by the openings of the film layer, the backside of the dies facing the surface of the heat sink;
allocating a first dielectric layer over the film layer and the active surface of the dies, the first dielectric layer patterned to form a plurality of first thru-holes that penetrate through the first dielectric layer and expose the metal pads of the dies; and
allocating a first patterned wiring layer over the first dielectric layer, the first patterned wiring layer electrically connected to the metal pads of the dies through the first thru-holes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
(a) allocating a second dielectric layer over the first dielectric layer and the first patterned wiring layer, the second dielectric layer patterned to form a plurality of second thru-holes that penetrate through the second dielectric layer; and
(b) allocating a second patterned wiring layer over the second dielectric layer, the second patterned wiring layer electrically connected to at least one of the dies through the second thru-holes.
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17. The method of claim 16, wherein the step of allocating the second patterned wiring layer over the second dielectric layer comprises filling the second thru-holes with part of a conductive material of the second patterned wiring layer to form a plurality of second vias, by which the second patterned wiring layer is electrically connected to the first patterned wiring layer.
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18. The method of claim 16, wherein before allocating the second patterned wiring layer on top of the second dielectric layer, the method comprises filling the second thru-holes with a conductive material to form a plurality of second vias, by which the second patterned wiring layer is electrically connected to the first patterned wiring layer.
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19. The method of claim 16, wherein a material of the second dielectric layer is selected from a group consisting of polyimide, benzocyclobutene, porous dielectric material, and stress buffer material.
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20. The method of claim 16, wherein the method of allocating the second patterned wiring layer on the second dielectric layer is selected from a group consisting of sputtering, electroplating, and electro-less plating.
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21. The method of claim 16, further comprising allocating a patterned passivation layer over the second dielectric layer and the second patterned wiring layer.
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22. The method of claim 16, wherein after allocating the second patterned wiring layer over the second dielectric layer, the method comprises allocating multiple bonding points over the second patterned wiring layer.
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23. The method of claim 22, wherein the bonding points are selected from a group consisting of solder balls, bumps, and pins.
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24. The method of claim 16, further comprising repeating step (a) and step (b) a plurality of times.
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25. The method of claim 24, further comprising allocating a patterned passivation layer over the second dielectric layer and the second patterned wiring layer that is furthest away from the substrate.
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26. The method of claim 16, wherein after allocating the second patterned wiring layer over the second dielectric layer, the method further comprises performing a singularizing process to form multiple chip package structures, each having a single die or a plurality of dies.
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27. The method of claim 26, wherein before performing a singularizing process and after allocating the second patterned wiring layer over the second dielectric layer, the method comprises allocating multiple bonding points over the second patterned wiring layer and the bonding points are selected from a group consisting of solder balls, bumps, and pins.
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28. A chip packaging method comprising:
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providing a first substrate with a first surface;
providing a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface;
mounting the dies over the first surface of the first substrate, the active surfaces of the dies facing the first surface of the first substrate;
thinning the dies from the backside;
providing a second substrate with a second surface;
mounting a second substrate over the backsides of the dies, the second surface of the second substrate facing the backsides of the dies;
removing the first substrate;
allocating a first dielectric layer over the second surface of the second substrate and the active surface of the dies, the first dielectric layer patterned to form a plurality of first thru-holes that penetrate through the first dielectric layer and expose the metal pads of the dies; and
allocating a first patterned wiring layer on the first dielectric layer, the first patterned wiring layer electrically connected to the metal pads of the dies through the first thru-holes. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
(a) allocating a second dielectric layer over the first dielectric layer and the first patterned wiring layer, the second dielectric layer patterned to form a plurality of second thru-holes that penetrate through the second dielectric layer; and
(b) allocating a second patterned wiring layer on the second dielectric layer, the second patterned wiring layer electrically connected to at least one of the dies through the second thru-holes.
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47. The method of claim 46, further comprising repeating step (a) and step (b) a plurality of times.
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48. The method of claim 47, further comprising allocating a patterned passivation layer on the second dielectric layer and the second patterned wiring layer that are furthest away from the second substrate.
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49. The method of claim 47, wherein after the second patterned wiring layer that are furthest away from the second substrate is allocated on the second dielectric layer, multiple bonding points are allocated on the second patterned wiring layer that is furthest away from the substrate.
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50. The method of claim 49, wherein the bonding points are selected from a group consisting of solder balls, bumps, and pins.
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51. The method of claim 49, wherein after allocating the bonding points on the second patterned wiring layer that are furthest away from the second substrate, the method further comprises performing a singularizing process to form multiple chip package structures, each having a single die or a plurality of dies.
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52. The method of claim 28, wherein a material of the second substrate is silicon.
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53. The method of claim 46, wherein the step of allocating the second patterned wiring layer on the second dielectric layer comprises filling the second thru-holes with part of a conductive material of the second patterned wiring layer to form a plurality of second vias, by which the second patterned wiring layer is electrically connected to the first patterned wiring layer.
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54. The method of claim 46, wherein before allocating the second patterned wiring layer on top of the second dielectric layer, the method comprises filling the second thru-holes with a conductive material to form a plurality of second vias, by which the second patterned wiring layer is electrically connected to the first patterned wiring layer.
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55. The method of claim 46, wherein a material of the second dielectric layer is selected from a group consisting of polyimide, benzocyclobutene, porous dielectric material, and stress buffer material.
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56. The method of claim 46, wherein a method of allocating the second patterned wiring layer on the second dielectric layer is selected from a group consisting of sputtering, electroplating, and electro-less plating.
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57. The method of claim 46, further comprising allocating a patterned passivation layer over the second dielectric layer and the second patterned wiring layer.
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58. The method of claim 46, wherein after allocating the second patterned wiring layer on the second dielectric layer, multiple bonding points are allocated on the second patterned wiring layer.
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59. The method of claim 58, wherein the bonding points are selected from a group consisting of solder balls, bumps, and pins.
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60. The method of claim 58, wherein after allocating the bonding points on the second patterned wiring layer, the method comprises performing a singularizing process to form multiple chip package structures, each having a single die or a plurality of dies.
Specification