High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidation

• US 6,746,925 B1
• Filed: 03/25/2003
• Issued: 06/08/2004
• Est. Priority Date: 03/25/2003
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Elmer, Jim, Gu, Shiqun, Lo, Wai, Lin, Hong
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US10/397,451
• Time in Patent Office: 441 Days
• Field of Search: 438/303, 438/585, 438/595, 438/772, 438/287
• US Class Current: 438/287
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/32105 Oxidation of silicon-containing layers

Abstract

In a method of forming an integrated circuit device, sidewall oxides are formed by plasma oxidation on the patterned gate. This controls encroachment beneath a dielectric layer underlying the patterned gate. The patterned gate is oxidized using in-situ O₂ plasma oxidation. The presence of the sidewall oxides minimizes encroachment under the gate edge.

Claims

1. A method of forming a semiconductor integrated circuit, the method comprising:

forming a dielectric layer on a substrate;

forming a gate conductive layer on the dielectric layer;

patterning and etching the gate conductive layer to form a gate electrode;

oxidizing the gate electrode using plasma oxidation to form a sidewall oxide;

etching the dielectric layer selectively such that a first region of the dielectric layer directly under the sidewall oxide is not etched; and

removing the sidewall oxide after etching the dielectric layer.

2. The method as recited in claim 1 wherein etching of the dielectric layer is performed using an anisotropic etch.

3. The method as recited in claim 1 wherein etching of the dielectric layer is performed using a plasma etch.

4. The method as recited in claim 1 wherein the thickness of the sidewall oxide formed is controlled by adjusting at least one of the oxidation time and plasma oxidation parameters.

5. The method as recited in claim 1 wherein the gate electrode is exposed to the plasma oxidation for a period in the range from 15 to 120 seconds.

6. The method as recited in claim 1 wherein thickness of the sidewall oxide formed is controlled by adjusting at least one of the plasma power, process chamber pressure, and substrate temperature.

7. The method as recited in claim 1 wherein the sidewall oxide thickness lies in the range from 3 nm to 10 nm.

8. The method as recited in claim 1 wherein the plasma oxidation occurs using an RF power source in the range of 100-1000 watts and an RF bias power source in the range of 0 to 20 watts coupled to the substrate support.

9. The method as recited in claim 1 wherein the plasma oxidation is performed by applying a higher RF power to the top RF electrode in the plasma process chamber and a lower bias RF power to the bottom electrode that is supporting the substrate.

10. The method as recited in claim 9 wherein the RF power applied to the top electrode lies in the range of 100-300 watts and the bias RF power applied to the bottom electrode lies in the range of 0-20 watts.

11. The method as recited in claim 1 wherein the plasma oxidation step is performed in-situ.

12. The method as recited in claim 9 wherein the RF power applied to the top electrode and the bias RF power applied to the bottom electrode are selected such that the ions from the plasma oxidation are not implanted into the substrate.

13. The method as recited in claim 1 wherein the dielectric layer is a high-k layer.

14. The method as recited in claim 1 wherein the dielectric layer comprises one of hafnium oxide, hafnium silicate, silicon nitride, and other metal oxides that contain at least one cation.

15. The method as recited in claim 1 wherein the dielectric layer comprises a nanolaminate.

16. The method as recited in claim 1 wherein the dielectric layer comprises zirconium oxide.

17. The method as recited in claim 1 wherein the gate is comprised of one of Poly-Si, amorphous Si, or Poly-SiGe.

18. The method as recited in claim 1 wherein the thickness of the sidewall oxide is selected to correspond to an expected penetration distance for lateral SiO₂ encroachment under the dielectric layer and into the substrate.

19. A method of forming a semiconductor integrated circuit, the method comprising:

forming a high-k dielectric layer on a substrate;

defining a gate electrode on the high-k dielectric layer;

forming a sidewall oxide on the gate electrode, the thickness of the sidewall oxide selected to correspond to an expected lateral penetration distance for SiO₂ bird'"'"'s beak encroachment under the high-k dielectric layer;

etching the high-k dielectric layer selectively such that a first region of the high-k dielectric layer directly under the sidewall oxide is not etched; and

removing the sidewall oxide after etching the high-k dielectric layer.