Semiconductor device with trench gate

• US 6,747,295 B2
• Filed: 01/16/2003
• Issued: 06/08/2004
• Est. Priority Date: 09/30/1999
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sugiyama, Koichi, Inoue, Tomoki, Ogura, Tsuneo, Ninomiya, Hideaki
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US10/345,268
• Publication Number:
  US 20030102486A1
• Time in Patent Office: 509 Days
• Field of Search: 257/124, 257/133, 257/137-139, 257/141, 257/330-331, 257/401, 257/146, 257/147, 257/328-333
• US Class Current: 257/139
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

An IGBT has a p-emitter layer and p-base layer, which are arranged on both sides of an n-base layer. A pair of main trenches are formed to extend through the p-base layer and reach the n-base layer. In a current path region interposed between the main trenches, a pair of n-emitter layers are formed on the surface of the p-base layer. A narrowing trench is formed to extend through the p-base layer and reach the n-base layer. The narrowing trench narrows a hole flow path formed from the n-base layer to the emitter electrode through the p-base layer, thereby increasing the hole current resistance.

Claims

1. A semiconductor device with a trench gate, comprising:

a first base layer of a first conductivity type;

a collector layer of a second conductivity type disposed on the first base layer;

a plurality of trenches disposed in the first base layer at intervals to partition a first main cell, a first dummy cell, a second main cell, and a second dummy cell in this order, at a position remote from the collector layer;

a second base layer of the second conductivity type disposed on the first base layer in each of the first and second main cells;

an emitter layer of the first conductivity type disposed on the second base layer;

a guard layer of the second conductivity type disposed on the first base layer in each of the first and second dummy cells;

a gate electrode disposed in each of the trenches to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;

a collector electrode disposed on the collector layer;

an emitter electrode disposed on the second base layer and the emitter layer; and

an insulating layer disposed on the guard layer and configured to prevent an electric current from flowing from the first base layer through the guard layer to the emitter electrode in an ON state of the device,

wherein each of the first and second main cells forms a current passage narrow enough to provide, in an on-state of the device, an increase in resistance against flow of carriers of the second conductivity type from the first base layer into the emitter electrode through the second base layer, thereby improving injection efficiency of carriers of the first conductivity type from the emitter layer into the first base layer, and

at least one of the first and second dummy cells comprises a deep guard layer as the guard layer, which has a resistivity lower than that of the second base layer, and is formed to at least a depth near bottom portions of the trenches, such that the first base layer and the deep guard layer form a pn-junction.

2. The device according to claim 1, wherein the deep guard layer occupies a substantially entire portion of said at least one of the first and second dummy cells.

3. The device according to claim 1, wherein the deep guard layer is substantially deeper than the second base layer.

4. The device according to claim 1, wherein the deep guard layer comprises a diffusion layer formed in a surface of the first base layer.

5. The device according to claim 1, wherein the guard layer is directly covered with the insulating layer in each of the first and second dummy cells.

6. The device according to claim 5, wherein an electrode portion integrated with the emitter electrode is disposed on the insulating layer in each of the first and second dummy cells.

7. The device according to claim 1, wherein the guard layer in each of the first and second dummy cells is not connected to the emitter electrode.