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Memory address decode array with vertical transistors

  • US 6,747,305 B2
  • Filed: 11/26/2002
  • Issued: 06/08/2004
  • Est. Priority Date: 08/04/1998
  • Status: Expired due to Fees
First Claim
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1. A memory device comprising:

  • a plurality of vertically stacked transistors outwardly extending away from a substrate, wherein the stacked transistors have a source region, a drain region, and a body region separating the source region and the drain region;

    at least one input conductor, wherein each of the at least one input conductor is formed lateral to the body region of at least one of the plurality of stacked transistors and functions as a gate for the at least one of the plurality of stacked transistors; and

    an output conductor coupled to the drain region of the at least one of the plurality of stacked transistors, wherein the output conductor is at least partially located in a vertical region above the input conductor.

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