Memory address decode array with vertical transistors
First Claim
1. A memory device comprising:
- a plurality of vertically stacked transistors outwardly extending away from a substrate, wherein the stacked transistors have a source region, a drain region, and a body region separating the source region and the drain region;
at least one input conductor, wherein each of the at least one input conductor is formed lateral to the body region of at least one of the plurality of stacked transistors and functions as a gate for the at least one of the plurality of stacked transistors; and
an output conductor coupled to the drain region of the at least one of the plurality of stacked transistors, wherein the output conductor is at least partially located in a vertical region above the input conductor.
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Abstract
A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number of vertical transistors are selectively disposed at intersections of output lines and address lines. Each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate. The vertical transistors each include source, drain, and body regions. A gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines. The transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
142 Citations
29 Claims
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1. A memory device comprising:
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a plurality of vertically stacked transistors outwardly extending away from a substrate, wherein the stacked transistors have a source region, a drain region, and a body region separating the source region and the drain region;
at least one input conductor, wherein each of the at least one input conductor is formed lateral to the body region of at least one of the plurality of stacked transistors and functions as a gate for the at least one of the plurality of stacked transistors; and
an output conductor coupled to the drain region of the at least one of the plurality of stacked transistors, wherein the output conductor is at least partially located in a vertical region above the input conductor. - View Dependent Claims (2, 3, 4)
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5. A memory device comprising:
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first and second vertically stacked transistors outwardly extending away from a substrate, wherein the first and second stacked transistors each have a source region, a drain region, and a body region separating the source region and the drain region;
a first input conductor formed lateral to the body region of the first stacked transistor such that the first input conductor functions as a gate for the first stacked transistor;
a second input conductor formed lateral to the body region of the second stacked transistor such that the second input conductor functions as a gate for the second stacked transistor; and
an output conductor coupled to the drain regions of the first and second stacked transistors, wherein the output conductor is at least partially located in a vertical region above the first and second input conductors. - View Dependent Claims (6, 7)
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8. A memory device, comprising:
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an array of vertically stacked transistors arranged in a number of columns and a number of rows, each stacked transistor in the array outwardly extending away from a substrate, each stacked transistor in the array including a first source/drain region formed on the substrate, a body region formed on the first source/drain region, a second source/drain region formed on the body region;
a number of input conductors including at least one input conductor disposed between two adjacent columns of the stacked transistors, the at least one input conductor to function as a gate for a first predetermined number of the stacked transistors in at least one of the two adjacent columns; and
a number of output conductors corresponding to the number of rows of vertically stacked transistors, each output conductor being connected to the second source/drain region of a second predetermined number of the stacked transistors in the corresponding rows of the stacked transistors, wherein the array of vertically stacked transistors, the number of input conductors, and the number of output conductors to implement a desired logic function for a signal supplied on the number of input conductors. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A memory device, comprising:
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an array of vertically stacked transistors arranged in a number of columns and a number of rows, each stacked transistor in the array outwardly extending away from a substrate, each stacked transistor in the array including a first source/drain region formed on the substrate, a body region formed on the first source/drain region, a second source/drain region formed on the body region;
a number of input conductors including one input conductor disposed between a first column and an adjacent second column of the stacked transistors and lateral to the body region of each of the stacked transistors in the first and second columns, the at least one input conductor to function as a gate for a first predetermined number of the stacked transistors in both the first and second columns; and
a number of output conductors corresponding to the number of rows of vertically stacked transistors, each output conductor being connected to the second source/drain region of at least one of the stacked transistors in the corresponding row of stacked transistors to respond to an input signal on the number of input conductors with a desired output signal on the number of output conductors. - View Dependent Claims (15, 16)
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17. A memory device, comprising:
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an array of vertically stacked transistors arranged in a number of columns and a number of rows, each stacked transistor in the array outwardly extending away from a substrate, each stacked transistor in the array including a first source/drain region formed on the substrate, a body region formed on the first source/drain region, a second source/drain region formed on the body region;
a number of input conductors including a first input conductor and a second input conductor disposed between a first column and an adjacent second column of the stacked transistors, the first input conductor being disposed lateral to the body region of each of the stacked transistors in the first column and the second input conductor being disposed lateral to the body region of the stacked transistors in the second column, the first input conductor to function as a gate for a first predetermined number of the stacked transistors in the first column and the second conductor to function as a gate for a second predetermined number of the stacked transistors in the second column; and
a number of output conductors corresponding to the number of rows of vertically stacked transistors, each output conductor being connected to the second source/drain region of at least one of the stacked transistors in the corresponding row of stacked transistors to respond to an input signal on the number of input conductors with a desired output signal on the number of output conductors. - View Dependent Claims (18, 19)
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20. A memory device, comprising:
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an array of vertically stacked transistors arranged in a number of columns and a number of rows, each stacked transistor in the array outwardly extending away from a substrate, each stacked transistor in the array including a first source/drain region formed on the substrate, a body region formed on the first source/drain region, a second source/drain region formed on the body region;
a number of input conductors interposed between adjacent columns of the stacked transistors, each of the number of input conductors to function as a gate for at least one of the stacked transistors in the array; and
a number of output conductors corresponding to the number of rows of stacked transistors, each output conductor being at least partially positioned over the number of input conductors, each output conductor being connected to the second source/drain region of at least one of the stacked transistors in the array. - View Dependent Claims (21, 22, 23, 24)
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25. A memory device, comprising:
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an array of vertically stacked transistors outwardly extending away from a substrate, each stacked transistor in the array including a first source/drain region, a second source/drain region, and a body region formed between the first source/drain region and the second source/drain region;
a number of output conductors, each output conductor connected to the second source/drain region of a number of stacked transistors; and
a number of address conductors coupled to receive an address signal, each address conductor to gate a predetermined number of stacked transistors in the array to provide a desired logic function to respond to the address signal by selecting at least one of the output conductors. - View Dependent Claims (26, 27, 28, 29)
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Specification