Combined transistor-capacitor structure in deep sub-micron CMOS for power amplifiers

• US 6,747,307 B1
• Filed: 04/04/2000
• Issued: 06/08/2004
• Est. Priority Date: 04/04/2000
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Sowlati, Tirdad, Vathulya, Vickram
• Primary Examiner(s): Wilson, Allan R.
• Assistant Examiner(s): BROCK II, PAUL E
• Application Number:
  US09/542,711
• Time in Patent Office: 1,526 Days
• Field of Search: 257/299, 257/306-309, 257/381, 257/382, 257/401, 257/532, 257/756, 257/758, 257/211, 257/206, 330/250, 330/251, 438/396-399, 438/253-256
• US Class Current: 257/307
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A combined transistor and capacitor structure comprising a transistor having alternating source and drain regions formed in a substrate of semiconductor material, and a capacitor formed over the transistor. The capacitor has at least first and second levels of electrically conductive parallel lines arranged in vertical rows, and at least one via connecting the first and second levels of lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. A dielectric material is disposed between the vertical plates of the array. The vertical array of capacitor plates are electrically connected to the alternating source and drain regions of the transistor which form opposing nodes of the capacitor and electrically interdigitate the vertical array of capacitor plates.

Claims

1. A combined transistor and capacitor structure comprising:

a transistor having a plurality of alternating source and drain regions formed in a substrate of semiconductor material; and

a capacitor formed over the transistor, the capacitor having;

at least first and second levels of electrically conductive parallel lines, the lines of the levels arranged in vertical rows, the lines in each of the rows being substantially parallel;

at least one via connecting the first and second levels of lines in each of the rows thereby forming a parallel array of vertical capacitor plates; and

a dielectric material disposed between the vertical plates of the array;

wherein the vertical array of capacitor plates are electrically connected to the plurality of alternating source and drain regions of the transistor, the source and drain regions forming opposing nodes of the capacitor, thereby electrically interdigitating the vertical array of capacitor plates.

2. The combined transistor and capacitor structure of claim 1, wherein the conductive lines comprise metal.

3. The combined transistor and capacitor structure of claim 1, wherein the conductive lines comprises polysilicon.

4. The combined transistor and capacitor structure of claim 1, wherein the dielectric material-comprises silicon dioxide.

5. The combined transistor and capacitor structure of claim 1, further comprising:

at least a third level of electrically conductive lines disposed over the second level of lines in manner which extends the rows vertically; and

at least one via connecting the second and third level lines in each of the rows so that the third level of lines vertically extends the parallel array of vertical capacitor plates.

6. The combined transistor and capacitor structure according to claim 1, wherein the transistor further includes:

a plurality of insulated gate structures disposed on the substrate between the source and drain regions;

a plurality of source and drain contacts electrically connecting the source and drain regions to the capacitor plates.

7. The combined transistor and capacitor structure according to claim 1, wherein the transistor is a power transistor.

8. The combined transistor and capacitor structure according to claim 1, wherein the transistor forms a power transistor of a Class E power amplifier in a sub-micron CMOS structure.

9. The combined transistor and capacitor structure according to claim 1, wherein the at least first and second levels of electrically conductive parallel lines comprise multiple levels of electrically conductive lines arranged in vertical rows, the lines in each of the rows being substantially parallel;

and the at least one via comprises a plurality of vias connecting the lines in each of the rows thereby forming a parallel array of vertical capacitor plates.

10. The combined transistor and capacitor structure according to claim 9, wherein the transistor further includes:

a plurality of insulated gate structures disposed on the substrate between the source and drain regions;

a plurality of source and drain contacts electrically connecting the source and drain regions to the capacitor plates.

11. A combined transistor and capacitor structure comprising:

a transistor having a source region and a drain region formed in a substrate of semiconductor material; and

a capacitor formed over the transistor, the capacitor having;

at least first and second levels of electrically conductive lines, the lines of the levels arranged in at least two vertical rows, the lines in each of the rows being substantially parallel;

at least one via connecting the first and second levels of lines in each of the rows thereby forming at least two parallel vertical capacitor plates; and

a dielectric material disposed between the vertical plates;

wherein one of the at least two capacitor plates is electrically connected to the source region of the transistor and other one of the at least two capacitor plates is electrically connected to the drain region of the transistor, the source and drain regions forming opposing nodes of the capacitor.