Method and apparatus for STI using passivation material for trench bottom liner

• US 6,747,333 B1
• Filed: 10/18/2002
• Issued: 06/08/2004
• Est. Priority Date: 02/26/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Xiang, Qi, Fisher, Philip A.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Mai, Anh Duy
• Application Number:
  US10/274,401
• Time in Patent Office: 599 Days
• Field of Search: 438/424, 438/221, 257/506, 257/510, 257/513
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material

Abstract

A silicon-on-insulator semiconductor device, including a silicon-on-insulator wafer having a silicon active layer, a dielectric isolation layer a silicon substrate, and at least one isolation trench defining an active island in the silicon active layer, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate, in which the at least one isolation trench includes a layer of a passivating insulator in a lower portion of the isolation trench and in contact with the dielectric insulation layer. The passivating insulator prevents formation of a bird'"'"'s beak between the silicon active layer and the dielectric insulation layer during subsequent fabrication of the isolation trench.

Claims

1. A silicon-on-insulator semiconductor device, comprising:

a silicon-on-insulator wafer having a silicon active layer, a dielectric insulation layer, a silicon substrate, and at least one isolation trench defining an active island in the silicon active layer, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate;

wherein the at least one isolation trench includes a layer of a passivating insulator in a lower portion of the isolation trench and in contact with the dielectric insulation layer, the passivating insulator having a depth sufficient to provide a protective shield or barrier whereby a bird'"'"'s beak cannot form between the silicon active layer and the dielectric insulation layer,

wherein the isolation trench above the passivating insulator is filled with a dielectric trench isolation material.

2. The silicon-on-insulator semiconductor device of claim 1, wherein each of the dielectric insulation layer, the passivating insulator and the dielectric trench isolation material comprise silicon dioxide.

3. The silicon-on-insulator semiconductor device of claim 1, wherein the trench isolation material is on the passivating insulator.

4. The silicon-on-insulator semiconductor device of claim 1, wherein the isolation trench further comprises a sidewall oxide liner.

5. The silicon-on-insulator semiconductor device of claim 1, wherein the isolation trench further comprises rounded upper corners.

6. The silicon-on-insulator semiconductor device of claim 1, wherein the device is free of a bird'"'"'s beak in the lower portion of the isolation trench between the silicon active layer and the dielectric insulation layer adjacent the isolation trench.

7. The silicon-on-insulator semiconductor device of claim 1, wherein the passivating insulator has a depth and width sufficient provide a protective shield or barrier to prevent formation of a bird'"'"'s beak in the lower portion of the isolation trench between the silicon active layer and the dielectric insulation layer adjacent the isolation trench.

8. The silicon-on-insulator semiconductor device of claim 1, wherein the passivating insulator comprises at least one of an oxide of silicon, a nitride of silicon, a mixture thereof or a mixed oxide and nitride of silicon.

9. The silicon-on-insulator semiconductor device of claim 1, wherein the passivating insulator forms an extension of the dielectric insulation material, the extension extending upward into the isolation trench, shielding a lower portion of the isolation trench, and preventing formation of a bird'"'"'s beak in the lower portion of the isolation trench between the silicon active layer and the dielectric isolation layer adjacent the isolation trench.

10. A silicon-on-insulator semiconductor device, comprising:

a silicon-on-insulator wafer having a silicon active layer, a dielectric insulation layer, a silicon substrate, and at least one isolation trench defining an active island in the silicon active layer, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate;

wherein the at least one isolation trench comprises rounded upper corners, a layer of a passivating insulator in a lower portion of the isolation trench and in contact with the dielectric insulation layer, a sidewall oxide liner, and a dielectric trench isolation material filling the isolation trench, the passivating insulator having a depth sufficient to provide a protective shield or barrier whereby a bird'"'"'s beak cannot form between the silicon active layer and the dielectric insulation layer.

11. The silicon-on-insulator semiconductor device of claim 10, wherein each of the dielectric insulation layer, the passivating insulator and the trench isolation material comprise silicon dioxide.

12. The silicon-on-insulator semiconductor device of claim 10, wherein the device is free of a bird'"'"'s beak in the lower portion of the isolation trench between the silicon active layer and the dielectric insulation layer adjacent the isolation trench.

13. The silicon-on-insulator semiconductor device of claim 10, wherein the passivating insulator has a depth and width sufficient provide a protective shield or barrier to prevent formation of a bird'"'"'s beak in the lower portion of the isolation trench between the silicon active layer and the dielectric insulation layer adjacent the isolation trench.

14. The silicon-on-insulator semiconductor device of claim 10, wherein the passivating insulator comprises at least one of an oxide of silicon, a nitride of silicon, a mixture thereof or a mixed oxide and nitride of silicon.

15. The silicon-on-insulator semiconductor device of claim 10, wherein the passivating insulator forms an extension of the dielectric insulation material, the extension extending upward into the isolation trench, shielding a lower portion of the isolation trench, and preventing formation of a bird'"'"'s beak in the lower portion of the isolation trench between the silicon active layer and the dielectric insulation layer adjacent the isolation trench.

16. A silicon-on-insulator semiconductor device, comprising:

a silicon-on-insulator wafer having a silicon active layer, a dielectric insulation layer, a silicon substrate, and at least one isolation trench defining an active island in the silicon active layer, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate;

wherein the at least one isolation trench comprises rounded upper corners, a layer of a passivating insulator in a lower portion of the isolation trench and in contact with the dielectric insulation layer, a sidewall oxide liner, and a dielectric trench isolation material filling the isolation trench, and the device is free of a bird'"'"'s beak in the lower portion of the isolation trench between the silicon active layer and the dielectric insulation layer adjacent the isolation trench, the passivating insulator having a depth sufficient to provide a protective shield or barrier whereby a bird'"'"'s beak cannot form between the silicon active layer and the dielectric insulation layer.

17. The silicon-on-insulator semiconductor device of claim 16, wherein the passivating insulator has a depth and width sufficient provide a protective shield or barrier to prevent formation of a bird'"'"'s beak in the lower portion of the isolation trench between the silicon active layer and the dielectric insulation layer adjacent the isolation trench.

18. The silicon-on-insulator semiconductor device of claim 16, wherein the passivating insulator comprises at least one of an oxide of silicon, a nitride of silicon, a mixture thereof or a mixed oxide and nitride of silicon.

19. The silicon-on-insulator semiconductor device of claim 16, wherein the passivating insulator forms an extension of the dielectric insulation material, the extension extending upward into the isolation trench, shielding a lower portion of the isolation trench, and preventing formation of a bird'"'"'s beak in the lower portion of the isolation trench between the silicon active layer and the dielectric insulation layer adjacent the isolation trench.