Differential memory interface system

• US 6,747,483 B2
• Filed: 05/01/2002
• Issued: 06/08/2004
• Est. Priority Date: 05/01/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: To, Hing Y, McCall, James A
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/136,920
• Publication Number:
  US 20030206046A1
• Time in Patent Office: 769 Days
• Field of Search: 326/80-83, 326/86-87, 326/63, 327/108, 327/109, 327/333
• US Class Current: 326/86
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A memory interface system comprising a differential control interface coupled with a first power supply, a common voltage supply and a buffer unit. The control interface is configured to drive a first and a second differential control output signal wherein the voltage output swing of the first and second differential control output signals is between a voltage output high level and the common voltage. The system also comprising a plurality of single-ended memory interfaces coupled with a second power supply, the common voltage supply and the buffer unit, wherein each memory interface is configured to drive a single-ended memory output signal to the common voltage to transfer a logic low, and the system also comprising the buffer unit coupled with the first power supply, the buffer unit configured to transfer data between the control interface and the memory interface.

Claims

1. A memory interface system comprising:

a differential control interface coupled with a first power supply, a common voltage supply and a buffer unit, wherein the differential control interface is configured to drive a first and a second differential control output signal, and wherein the voltage output swing of the first and second differential control output signals is between a voltage output high level and the common; and

a plurality of single-ended memory interfaces coupled with a second power supply, the common voltage supply and the buffer unit, wherein each single-ended memory interface is configured to drive a single-ended memory output signal to the common voltage to transfer a logic low, wherein the buffer unit is coupled with the first power supply, and the buffer unit is configured to transfer data between the differential control interface and the single-ended memory interface.

2. The system of claim 1, wherein the first power supply operates at a lower voltage than the second power supply.

3. The system of claim 1, wherein the common supply is ground.

4. The system of claim 1, wherein the buffer unit is configured to:

convert the first and second differential control output signals to a single-ended control output signal; and

output the single-ended control output signal to the single-ended memory interface.

5. The system of claim 1, wherein the buffer unit is configured to:

convert the single-ended memory output signal to a first and a second differential memory output signal; and

output the first and second differential memory output signal to the differential control interface.

6. The system of claim 1, wherein each single-ended memory interface comprises a memory driver configured to drive the single-ended memory output signal and wherein the differential control interface comprises a control driver configured to drive the first and second differential control output signals.

7. The system of claim 6, wherein the control driver comprises a resistive bias circuit configured to track output current output current of the control driver.

8. The system of claim 5, wherein the differential control interface comprises a control receiver configured to receive the first and second differential memory output signals from the buffer unit, and wherein the plurality of single-ended memory interfaces each comprise a memory receiver configured to receive the single-ended control output signal from the buffer unit.

9. A memory interface system for transferring data, the system comprising a control driver configured to drive a first and a second control output signal, the control driver comprising:

a first current source coupled with a first power supply, the first current source

configured to provide a control output current;

a first switching unit coupled with the first current source, the first switching unit configured to switch based on a first control input signal;

a first resistive bias unit coupled with the first switching unit, the first resistive bias unit configured to track the control output current;

a first bus coupled between the first switching unit and the first resistive bias unit, wherein the first control output signal is the voltage level between the first switching unit and first resistive bias unit;

a second switching unit coupled with the first current source, the second switching unit configured to switch based on a second control input signal;

a second resistive bias unit coupled with the second switching unit, the second resistive bias unit configured to track the control output current;

a second bus coupled between the second switching unit and the second resistive bias unit, wherein the second control output signal is the voltage level between the second switching unit and second resistive bias unit.

10. The system of claim 9, further comprising a pre-driver circuit configured to convert a first differential data signal and a second differential data signal to the first control input signal and the second control input signal, respectively.

11. The system of claim 9, wherein the first resistive bias unit comprises a first sense amplifier and wherein the second resistive bias unit comprises a second sense amplifier, the first and second sense amplifiers configured to track the control output current.

12. The system of claim 9, wherein the first and second switching units each comprise a P-type transistor.

13. The system of claim 9, wherein the first current source comprises a P-type transistor.

14. A memory interface system for transferring data, the system comprising a control driver configured to drive a first and a second control output signal, the control driver comprising:

a first current source coupled with a first power supply, the first current source configured to provide a control output current;

a first switching unit coupled with the first current source, the first switching unit configured to switch based on a first control input signal;

a first resistive bias unit coupled with the first switching unit, the first resistive bias unit configured to track the control output current;

a first bus coupled between the first switching unit and the first resistive bias unit, wherein the first control output signal is the voltage level between the first switching unit and first resistive bias unit;

a second switching unit coupled with the first current source, the second switching unit configured to switch based on a second control input signal;

a second resistive bias unit coupled with the second switching unit, the second resistive bias unit configured to track the control output current;

a second bus coupled between the second switching unit and the second resistive bias unit, wherein the second control output signal is the voltage level between the second switching unit and second resistive bias unit, wherein the first and second buses are coupled to a buffer unit configured to convert the first and second differential control output signals to a single-ended control output signal and the buffer unit is further configured to output the single-ended control output signal to a memory interface over a third bus.

15. The system of claim 14, wherein the memory interface comprises a memory driver, the memory driver configured to drive a memory output signal, the memory driver comprising:

a second current source coupled with a second power supply;

a third switching unit coupled with the second current source, the third switching unit configured to switch based on a memory input signal; and

the third bus coupled with the second switching unit, the buffer unit and a termination resistor, wherein the memory output signal is the voltage level output by the third switching unit.

16. The system of claim 15, wherein the third switching unit and the second current source each comprise a P-type transistor.

17. A memory interface system for transferring data, the system comprising a control driver configured to drive a first and a second control output signal, the control driver comprising:

a first current source coupled with a first power supply, the first current source configured to provide a control output current;

a first switching unit coupled with the first current source, the first switching unit configured to switch based on a first control input signal;

a first resistive bias unit coupled with the first switching unit, the first resistive bias unit configured to track the control output current;

a first bus coupled between the first switching unit and the first resistive bias unit, wherein the first control output signal is the voltage level between the first switching unit and first resistive bias unit;

a second switching unit coupled with the first current source, the second switching unit configured to switch based on a second control input signal;

a second resistive bias unit coupled with the second switching unit, the second resistive bias unit configured to track the control output current;

a second bus coupled between the second switching unit and the second resistive bias unit, wherein the second control output signal is the voltage level between the second switching unit and second resistive bias unit; and

a first pre-driver circuit and a second pre-driver circuit, the first pre-driver circuit configured to control a data edge rate of the first control input signal and the second pre-driver circuit configured to control a data edge rate of the second control input signal.

18. A memory interface system, comprising:

a memory control hub configured to transfer data to a memory module by way of a buffer unit, the memory control hub comprising a control interface coupled to a first power supply and a common voltage supply, the control interface configured to drive a first and a second differential control output signal, wherein the voltage output swing of the first and second differential control output signals is between a differential voltage output level and the common voltage; and

the memory module comprising a plurality of memory interfaces, each memory interface coupled to a second power supply, a common supply and the buffer unit, and each memory interface configured to drive a single-ended memory output signal to the buffer unit, wherein the single-ended memory output signal is driven to a voltage output high level to transfer a logic high, and the single-ended memory output signal is driven to the common supply voltage to transfer a logic low.

19. The system of claim 18, wherein:

the control interface comprises a control driver configured to drive the first and second differential control output signal, the control driver comprising a first resistive bias unit and second resistive bias unit configured to track the control output current, and a control receiver configured to receive the single-ended memory output signal; and

the memory interface comprises a memory driver configured to drive the single-ended memory output signal, and a memory receiver configured to receive the single-ended control output signal.

20. The system of claim 18, wherein the common supply is set to ground.

21. The system of claim 18, wherein the buffer unit is configured to:

convert the first and second differential control output signals to a single-ended control output signal;

output the single-ended control output signal to a selected memory interface;

convert the single-ended memory output signal to a first and a second differential memory output signal; and

output the first and second differential memory output signal to the control interface.