Charge pump architecture

• US 6,747,506 B1
• Filed: 12/20/2002
• Issued: 06/08/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Thiara, Raman S.
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US10/325,051
• Publication Number:
  US 20040119513A1
• Time in Patent Office: 536 Days
• Field of Search: 327/537, 327/536, 327/437, 327/157, 327/158, 327/105, 327/156
• US Class Current: 327/537
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses

Abstract

According to some embodiments, a charge pump includes a first transistor to steer an amount of current to a second transistor coupled to the first transistor in a first folded cascode arrangement and to a current mirror to sink substantially the amount of current from a load, and a third transistor to steer the amount of current to a fourth transistor coupled to the third transistor in a second folded cascode arrangement to source substantially the amount of current to the load.

Claims

1. A charge pump comprising:

a first transistor of a first type, a gate of the first transistor to receive a first component of a first differential charge pump control signal;

a second transistor of a second type, a source of the second transistor coupled to a drain of the first transistor, and a drain of the second transistor coupled to an output node;

a third transistor of the first type, a gate of the third transistor to receive a first component of a second differential charge pump control signal;

a fourth transistor of the second type, a source of the fourth transistor coupled to a drain of the third transistor; and

a current mirror, an input of the current mirror coupled to a drain of the fourth transistor and an output of the current mirror coupled to the output node,

wherein, in response to receipt of the first component of the first differential charge pump control signal in a first state, the first transistor is to steer an amount of current through the second transistor to source substantially the amount of current to the output node, and

wherein, in response to receipt of the first component of the second differential charge pump control signal in the first state, the third transistor is to steer the amount of current through the fourth transistor to the input of the current mirror to sink the amount of current from the output node.

2. A charge pump according to claim 1,

wherein the first differential charge pump control signal is an UP signal, and wherein the second differential charge pump control signal is a DOWN signal.

3. A charge pump according to claim 1,

wherein the first differential charge pump control signal is a DOWN signal, and wherein the second differential charge pump control signal is an UP signal.

4. A charge pump according to claim 1,

wherein the first type is NMOS and wherein the second type is PMOS.

5. A charge pump according to claim 1,

wherein the first type is PMOS and wherein the second type is NMOS.

6. A charge pump according to claim 1,

wherein the current mirror comprises transistors of the first type.

7. A charge pump according to claim 1, further comprising:

a current source to output a current based on a common-mode feedback voltage signal.

8. A charge pump according to claim 1, further comprising:

a fifth transistor of the first type to receive a second component of the first differential charge pump control signal, a source of the fifth transistor coupled to a source of the first transistor and to a first current source, and a drain of the fifth transistor coupled to a supply voltage; and

a sixth transistor of the first type to receive a second component of the second differential charge pump control signal, a source of the sixth transistor coupled to a source of the third transistor and to a second current source, and a drain of the sixth transistor coupled to the supply voltage.

9. A system comprising:

a transceiver comprising a charge pump, the charge pump comprising;

a first transistor of a first type, a gate of the first transistor to receive a first component of a first differential charge pump control signal;

a second transistor of a second type, a source of the second transistor coupled to a drain of the first transistor, and a drain of the second transistor coupled to an output node;

a third transistor of the first type, a gate of the third transistor to receive a first component of a second differential charge pump control signal;

a fourth transistor of the second type, a source of the fourth transistor coupled to a drain of the third transistor; and

a current mirror, an input of the current mirror coupled to a drain of the fourth transistor and an output of the current mirror coupled to the output node,

wherein, in response to receipt of the first component of the first differential charge pump control signal in a first state, the first transistor is to steer an amount of current through the second transistor to source substantially the amount of current to the output node, and

wherein, in response to receipt of the first component of the second differential charge pump control signal in the first state, the third transistor is to steer the amount of current through the fourth transistor to the input of the current mirror to sink the amount of current from the output node; and

an optical interface coupled to the transceiver to receive and to transmit optical signals.

10. A system according to claim 9, further comprising:

a backplane interface coupled to the transceiver to receive and transmit electrical signals to a backplane.