High speed data bus
First Claim
Patent Images
1. A memory module comprising:
- a printed circuit board;
a first plurality of electrical contacts arranged on said printed circuit board to connect to a data bus;
a second plurality of electrical contacts arranged on said printed circuit board to connect to memory control signals for performing memory access cycles, said memory control signals including a row address strobe signal and a column address strobe signal;
at least one memory integrated circuit attached to said printed circuit board and receiving one or more memory control signals from said second plurality of electrical contacts;
a state decoder circuit separate from said memory integrated circuit having an input coupled to at least some of said memory control signals and an output, wherein said state decoder circuit is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access; and
at least one switch having a plurality of inputs connected to corresponding ones of said first plurality of electrical contacts, and a plurality of outputs connected to said at least one memory integrated circuit so as to couple said data bus from said first plurality of electrical contacts to said memory integrated circuit, said at least one switch having an additional input coupled to said state decoder circuit output, and responsive to said state decoder circuit output to decouple said memory circuit from said data bus when no memory access cycle is being performed.
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Abstract
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.
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Citations
12 Claims
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1. A memory module comprising:
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a printed circuit board;
a first plurality of electrical contacts arranged on said printed circuit board to connect to a data bus;
a second plurality of electrical contacts arranged on said printed circuit board to connect to memory control signals for performing memory access cycles, said memory control signals including a row address strobe signal and a column address strobe signal;
at least one memory integrated circuit attached to said printed circuit board and receiving one or more memory control signals from said second plurality of electrical contacts;
a state decoder circuit separate from said memory integrated circuit having an input coupled to at least some of said memory control signals and an output, wherein said state decoder circuit is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access; and
at least one switch having a plurality of inputs connected to corresponding ones of said first plurality of electrical contacts, and a plurality of outputs connected to said at least one memory integrated circuit so as to couple said data bus from said first plurality of electrical contacts to said memory integrated circuit, said at least one switch having an additional input coupled to said state decoder circuit output, and responsive to said state decoder circuit output to decouple said memory circuit from said data bus when no memory access cycle is being performed. - View Dependent Claims (2, 3)
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4. A printed circuit board, comprising:
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a first plurality of electrical contacts arranged on said printed circuit board to connect to a data bus;
a second plurality of electrical contacts arranged on said printed circuit board to connect to memory control signals for performing memory access cycles, said memory control signals including a row address strobe signal and a column address strobe signal;
at least one memory integrated circuit attached to said printed circuit board and receiving one or more memory control signals from said second plurality of electrical contacts;
a state decoder circuit separate from said memory integrated circuit having an input coupled to at least some of said memory control signals and an output, wherein said state decoder circuit is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access; and
at least one switch having a plurality of inputs connected to corresponding ones of said first plurality of electrical contacts, and a plurality of outputs connected to said at least one memory integrated circuit so as to couple said data bus from said first plurality of electrical contacts to said memory integrated circuit, said at least one switch having an additional input coupled to said state decoder circuit output, and responsive to said state decoder circuit output to decouple said memory circuit from said data bus when no memory access cycle is being performed. - View Dependent Claims (5, 6)
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7. A state decoder circuit, comprising:
a state decoder for receiving a chip select signal targeted for a memory circuit and having an input coupled to memory control signals and an output, wherein said state decoder is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access, and wherein the state decoder is configured to activate a switch to decouple a memory circuit from a data bus when no memory access cycle is being performed. - View Dependent Claims (8, 9, 10)
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11. A switch, comprising:
a plurality of inputs connected to corresponding ones of first plurality of electrical contacts, and a plurality of outputs connected to at least one memory integrated circuit so as to couple a data bus from said first plurality of electrical contacts to said memory integrated circuit, said at least one switch having an additional input coupled to a state decoder circuit output that is responsive to a chip select signal, and responsive to said state decoder circuit output to decouple said memory circuit from said data bus when no memory access cycle is being performed. - View Dependent Claims (12)
Specification