Automatic gain control system and method for a ZIF architecture

• US 6,748,200 B1
• Filed: 04/04/2003
• Issued: 06/08/2004
• Est. Priority Date: 10/02/2000
• Status: Expired due to Term

• Current Assignee: M-Red Inc. (Quest Patent Research Corporation)
• Original Assignee: Conexant Incorporated (Synaptics Incorporated)
• Inventors: Webster, Mark A., Yeh, Alex C., Garrett, Albert L.
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): LE, LANA N
• Application Number:
  US10/407,350
• Time in Patent Office: 431 Days
• Field of Search: 455/232.1, 455/234.1, 455/234.2, 455/324, 455/323, 455/296, 455/313, 455/226.1, 455/341, 455/127--12, 455/250.1, 455/78, 375/341, 375/345
• US Class Current: 455/234.1
• CPC Class Codes: H03D 2200/0047 Offset of DC voltage or frequency
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H03D 3/009 Compensating quadrature phase or amplitude imbalances
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A system and method for controlling amplification of a signal received by a ZIF radio having a power level within a full power range relative to a minimum noise floor. The ZIF radio includes a ZIF receiver front end, an overload detector, an ADC, a saturation detector, a DC and power estimator, and control logic. The control logic utilized full visibility of the ADC to limit gain of the baseband amplifier to a maximum gain setting sufficient to view the minimum noise floor and to view a received signal having a power level within any of several segments of the power spectrum. The segmentation of the power spectrum is based on an overload condition of the ZIF receiver front end and a saturation condition of the ADC. The control logic further employs limited gain stepping of the baseband amplifier to avoid exceeding a DC budget of the ADC.

Claims

1. A method of controlling amplification of a signal received by a ZIF radio having a power level within a predetermined full power range relative to a predetermined minimum noise floor, comprising:

amplifying the received signal using a baseband amplifier with a plurality of gain settings;

converting the received signal to a digital signal using an analog to digital converter (ADC); and

controlling said amplifying of the received signal for tracking noise floor and for attempting to acquire the received signal while limiting DC change within an available DC budget of the ADC, said controlling comprising;

obtaining actual noise floor level by setting gain up to a maximum gain level within a first story power range at a lower end of the full power range sufficient for the ADC to view the minimum noise floor;

detecting an overload condition and switching gain in a single gain step to within a third story power range at an upper end of the full power range sufficient for the ADC to view the received signal; and

detecting a saturation condition of the ADC and switching gain in a single gain step to within a second story power range between the first and second story power ranges sufficient for the ADC to view the received signal.

2. The method of claim 1, wherein said obtaining actual noise floor level comprises switching the baseband amplifier up to a predetermined maximum gain setting using limited gain stepping to avoid exceeding the DC budget of the ADC.

3. The method of claim 2, further comprising:

settling after each said switching;

after each said settling, measuring DC of the digital signal and subtracting measured DC from the received signal; and

after a final of said switching and settling, measuring power level of the digital signal.

4. The method of claim 3, wherein each occurrence of said measuring DC before a last occurrence of said measuring DC comprises short interval measurements and wherein the last occurrence of said measuring DC and said measuring power level comprises a long interval measurement.

5. The method of claim 2, wherein said amplifying the received signal comprises using an RF amplifier with high and low gain settings and wherein said obtaining an actual noise floor level includes switching the RF amplifier to its high gain setting.

6. The method of claim 1, further comprising:

detecting a signal trigger condition in which power level is increased over the actual noise floor by at least a predetermined signal trigger threshold;

measuring power level and DC level of the digital signal in response to detecting any one of the overload, saturation and signal trigger conditions;

if measured power level of the digital signal is greater than a predetermined target back-off power level of the ADC, switching the baseband amplifier and subtracting DC from the received signal and settling;

verifying power level and measuring DC level of the digital signal; and

subtracting any remaining DC offset from the received signal and settling.

7. The method of claim 6, further comprising:

said verifying power level comprising measuring power level of the digital signal and comparing with a target back-off power level for the ADC; and

if the digital signal power level is outside tolerance of the target back-off power level, switching the baseband amplifier towards the target back-off power level up to its maximum gain setting and settling again, and repeating said verifying power level.

8. The method of claim 7, wherein each said measuring power level and DC level of the digital signal comprises a long interval measurement.

9. The method of claim 6, further comprising digitally amplifying the digital signal to achieve a power level equivalent to the target back-off power level of the ADC if the baseband amplifier is at its maximum gain setting and the power level of the digital signal is less than the target back-off power level of the ADC.

10. The method of claim 6, further comprising:

said amplifying the received signal comprising using an RF amplifier with high and low gain settings; and

switching the RF amplifier to its low gain setting in response to said detecting an overload condition.

11. A ZIF radio for detecting an RF signal within a predetermined power spectrum relative to a predetermined minimum noise floor, comprising:

a ZIF receiver front end that converts the RF signal to a baseband signal and that includes a baseband amplifier;

an overload detector, coupled to said ZIF receiver front end, that detects an overload condition of said ZIF receiver front end in which said RF signal is within an upper power range of a predetermined power spectrum and that asserts an overload signal indicative thereof;

an analog to digital converter (ADC), coupled to said ZIF receiver front end, that converts said baseband signal to a digital baseband signal;

a saturation detector, coupled to said ADC, that detects a saturation condition of said ADC in which said RF signal is within a middle power range of the power spectrum and that provides a saturation signal indicative thereof;

a DC and power estimator, coupled to said ADC, that estimates DC and power level of said digital baseband signal and that provides estimation signals indicative thereof; and

control logic, coupled to said saturation detector, said overload detector and said DC and power estimator and operatively coupled to said ZIF receiver front end via AGC and DC loops, that limits gain of said baseband amplifier to a maximum gain setting sufficient for said ADC to view a lower power story including the minimum noise floor of the power spectrum, that monitors said saturation, overload and estimation signals, and that switches gain of said baseband amplifier once to place the received signal within view of said ADC in the event of either one of said overload and saturation conditions.

12. The control system of claim 11, wherein said ZIF receiver front end comprises:

an RF amplifier having high and low gain settings for amplifying the RF signal;

a mixer, coupled to said RF amplifier, that converts said RF signal to said baseband signal;

a DC combiner, coupled to said mixer, that subtracts a DC offset from said baseband signal; and

wherein said overload detector is coupled to said RF amplifier for detecting said an overload condition, and wherein said control logic is operative to switch said RF amplifier to its low gain setting in the event of said overload condition.

13. The control system of claim 12, further comprising a digital amplifier, coupled to said control logic and said ADC, that is controlled by said control logic to digitally amplify said digital baseband signal to obtain a target back-off power level of the ADC if the digital baseband signal is less than said target back-off power level and the baseband amplifier is at said maximum gain setting.

14. The control system of claim 11, wherein the control logic is operative to command said DC and power estimator to make a short interval measurement for speed and to make a long interval measurement for accuracy.

15. The control system of claim 14, wherein said control logic is operative to obtain an actual noise floor level upon initialization or after prior signal acquisition by switching gain of said baseband amplifier up to said maximum gain setting and delaying for settling after each switching, by commanding a short interval measurement of DC offset after each of initial gain switches and a long interval measurement of power and DC after a last gain switching, and by subtracting a measured DC offset via said DC combiner for each gain switching.

16. The control system of claim 15, wherein said control logic delays by approximately 800 nanoseconds for each settling, wherein said short interval measurement is approximately 200 nanoseconds and wherein said long interval measurement is approximately 800 nanoseconds so that said actual noise floor level is obtained within approximately 4.4 microseconds.

17. The control system of claim 14, wherein said control logic is operative to acquire said baseband signal after said overload condition is detected by switching gain of said baseband amplifier once to place total gain within said upper power range and then delaying for settling, by commanding a long interval measurement of DC and power, by again subtracting DC offset and switching gain and delaying for settling, and by commanding another long interval measurement of DC and power for power verification and subtracting any additional DC offset and delaying for settling.

18. The control system of claim 17, further comprising:

said ZIF receiver front end further comprises an RF amplifier having high and low gain settings for amplifying the RF signal; and

said control logic further operative to switch said RF amplifier to said low gain setting after said overload condition is detected.

19. The control system of claim 17, wherein said control logic is operative to acquire said baseband signal after said saturation condition is detected by first switching gain of said baseband amplifier once to place total gain within said middle power range and delaying for settling, by commanding a long interval measurement of DC and power, by again subtracting DC offset and switching gain and delaying for settling, and by commanding another long interval measurement of DC and power for power verification and subtracting any additional DC offset and delaying for settling.

20. The control system of claim 19, further comprising:

a digital amplifier, coupled to said control logic and said ADC;

wherein said control logic is operative to attempt to acquire said baseband signal after detection of a signal trigger condition in which the power level of said baseband signal increases above a signal trigger threshold, by commanding a long interval measurement of DC and power, by subtracting DC offset and switching gain if necessary for signal acquisition and delaying for settling after switching, and by commanding another long interval measurement of DC and power for power verification and subtracting any additional DC offset and delaying for settling; and

wherein if said baseband signal is amplified less than a target back-off level of said ADC when said baseband amplifier is at said maximum gain setting, said control logic is operative to control said digital amplifier to further amplify said digital baseband signal.

21. The control system of claim 20, wherein said control logic is operative to repeat subtracting DC offset and switching gain and delaying for settling in the event power verification fails and repeating said commanding another long interval measurement of DC and power for power verification and subtracting DC offset and delaying for settling.

22. The control system of claim 20, wherein said overload condition is detected within approximately 800 nanoseconds of signal onset, wherein said saturation and signal trigger conditions are detected within approximately 1.6 microseconds of signal onset, and wherein said long interval measurement is approximately 800 nanoseconds so that said baseband signal is acquired within approximately 6.4 microseconds.

23. A processing system with wireless communications, comprising:

a processor;

a memory coupled to said processor; and

a ZIF transceiver, communicatively coupled to said processor, that detects RF signals within a predetermined full power spectrum, comprising;

a ZIF receiver front end including a low noise amplifier (LNA), a DC subtractor and a baseband amplifier;

an analog to digital converter (ADC), coupled to said ZIF receiver front end, that converts said baseband signal to a digital baseband signal;

a saturation detector, coupled to said ADC, that detects a saturation condition of said ADC indicative of a medium-powered signal;

an overload detector, coupled to said ZIF receiver front end, that detects an overload condition of the baseband signal indicative of a strong signal;

a joint DC and power estimator, coupled to said ADC, that estimates DC and power level of said digital baseband signal; and

AGC/DC control logic, coupled to said ZIF receiver front end, said overload detector, and said joint DC and power estimator, that employs full utilization of visibility of said ADC to limit gain of said baseband amplifier to a maximum gain setting and to segment said full power spectrum based on said overload and saturation conditions, and that employs limited gain stepping to avoid exceeding a DC budget of said ADC when switching gain of said baseband amplifier.

24. The processing system of claim 23, wherein said AGC/DC control logic controls said joint DC and power estimator to make a short interval measurement for speed and to make a long interval measurement for accuracy.

25. The processing system of claim 23, wherein said AGC/DC control logic controls gain of said ZIF receiver front end to perform each of a plurality of tasks within 6.4 microseconds, said tasks including obtaining actual noise floor and signal acquisition.

26. The processing system of claim 23, wherein said ADC has a visible power range of approximately 30 decibels.

27. The processing system of claim 23, wherein said ZIF transceiver is implemented as an expansion unit for coupling to a host system incorporating said processor and memory.

28. The processing system of claim 27, wherein said host system comprises a computer system.

29. The processing system of claim 23, wherein said processor, memory and ZIF transceiver collectively implement a standalone unit.

30. The processing system of claim 29, wherein said standalone unit comprises a wireless access point.