Mixer noise reduction technique

• US 6,748,204 B1
• Filed: 10/17/2000
• Issued: 06/08/2004
• Est. Priority Date: 10/17/2000
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Zhang, Pengfei, Razavi, Behzad
• Primary Examiner(s): Tran, Sinh
• Assistant Examiner(s): Nguyen, David Q
• Application Number:
  US09/691,297
• Time in Patent Office: 1,330 Days
• Field of Search: 455/323, 455/326, 455/330, 455/333, 455/337, 327/355, 330/253, 330/254, 330/261, 330/252
• US Class Current: 455/296
• CPC Class Codes: H03D 2200/0043 Bias and operating point
• CPC Class Codes: H03D 7/1433 using bipolar transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence

Abstract

In accordance with the present invention a mixer circuit noise reduction technique is provided. The mixer circuit of the present invention includes a gain stage for receiving a first signal and producing an output signal. The mixer circuit also includes a bias circuit coupled to the gain stage through a common node for providing a bias current to the gain stage, the bias circuit having an input for receiving a second signal, and in accordance therewith, varying the bias current. Additionally, the mixer circuit includes a frequency dependent current shunt circuit coupled between the common node and a reference voltage, wherein a first portion of the bias current frequency components within a first frequency range are coupled to the reference voltage by the shunt circuit, and a second portion of the bias current frequency components within a second frequency range are coupled to the reference voltage by the shunt circuit, the first portion being larger than the second portion. As a result, the noise in the mixer circuit is reduced while the gain is enhanced.

Claims

1. A mixer circuit comprising:

a gain stage configured to receive a first signal and a bias current, and in accordance therewith, produce an output signal, the gain stage receiving the bias current on a common node;

a bias circuit having an input configured to receive a second signal and an output coupled to the common node to provide the bias current to the gain stage, the bias current comprising bias current frequency components; and

a frequency dependent current shunt circuit coupled between the common node and a reference voltage, wherein a first portion of the bias current frequency components within a first frequency range are coupled to the reference voltage by the shunt circuit, and a second portion of the bias current frequency components within a second frequency range are coupled to the reference voltage by the shunt circuit, the first portion being larger than the second portion,

wherein the second frequency range is higher than the first frequency range.

2. The mixer circuit of claim 1 wherein the second signal generates a first frequency component in the bias current, the first frequency component being within the second frequency range.

3. The mixer circuit of claim 1 wherein the bias current received by the gain stage is reduced, and in accordance therewith, noise in the output signal is reduced.

4. The mixer circuit of claim 1 wherein the second signal includes an RF frequency and the second frequency range is a high frequency range, the RF frequency of the second signal being within the high frequency range.

5. The mixer circuit of claim 1 wherein the second portion of the frequency components coupled to the reference voltage by the shunt circuit is substantially zero.

6. The mixer circuit of claim 1 wherein the frequency dependent current shunt circuit comprises an inductor having a first terminal coupled to the common node and a second terminal coupled to the reference voltage.

7. The mixer circuit of claim 6 wherein the frequency dependent current shunt circuit further comprises a resistor coupled between the common node and the first terminal of the inductor.

8. The mixer circuit of claim 1 wherein the bias circuit comprises a transistor having a control input and a first and second output, wherein the control input is coupled to a bias voltage, the first output is coupled to a second reference voltage, and the second output is coupled to the common node.

9. The mixer circuit of claim 8 wherein the second output of the transistor is coupled to receive the second signal.

10. The mixer circuit of claim 8 wherein the transistor is an NMOS transistor.

11. The mixer circuit of claim 1 wherein the gain stage is a differential stage and the first signal is a differential signal.

12. The mixer circuit of claim 11 wherein the differential stage comprises:

a first transistor having a control input and first and second outputs, the control input coupled to receive a first component of the differential signal;

a second transistor having a control input and first and second outputs, the control input coupled to receive a second component of the differential signal; and

a load coupled to the first output of the first transistor and to the first output of the second transistor,

wherein the second output of the first transistor and the second output of the second transistor are coupled together and to the common node.

13. The mixer circuit of claim 12 wherein the first and second transistors are NMOS transistors.

14. The mixer circuit of claim 12 wherein the load comprises a first resistor coupled between the first output of the first transistor and a supply voltage and a second resistor coupled between the first output of the second transistor and the supply voltage.

15. The mixer circuit of claim 1 wherein the reference voltage is a supply voltage.

16. A mixer circuit comprising:

first and second transistors configured to receive a differential input signal, the first and second transistors coupled to a common node to receive a bias current;

a third transistor having a bias output coupled to the common node, the third transistor coupled to receive an RF signal and generate a bias current at the bias output; and

an inductor having a first terminal coupled to the common node and a second terminal coupled to a supply voltage;

wherein the bias current comprises bias frequency components, and a frequency dependent current shunt circuit couples a first portion of the bias current frequency components within a first frequency range to the supply voltage, and couples a second portion of the bias current frequency components within a second frequency range to the supply voltage, the first portion being larger than the second portion.

17. The mixer circuit of claim 16 further comprising a first resistor coupled between the first transistor and the supply voltage and a second resistor coupled between the second transistor and the supply voltage.

18. The mixer circuit of claim 16 further comprising a resistor coupled between the common node and the first terminal of the inductor.

19. The mixer circuit of claim 16 wherein the inductor is integrated on a semiconductor substrate and includes a parasitic capacitance coupled between the inductor and the supply voltage.

20. The mixer circuit of claim 16 wherein the inductor is integrated on a semiconductor substrate and includes a parasitic resistance coupled between the first terminal of the inductor and the supply voltage.

21. The mixer circuit of claim 16 wherein the RF signal is coupled to the bias output and to the common node.

22. The mixer circuit of claim 16 wherein the first, second, and third transistors are NMOS transistors.

23. A method of reducing noise in a mixer comprising:

receiving a first signal in a gain stage;

receiving a second signal in a bias circuit, the second signal having a first frequency;

generating a bias current in response to the second signal, the bias current having bias current frequency components including a frequency component at the first frequency;

shunting a first portion of the bias current frequency components within a first frequency range to a reference voltage and a second portion of the bias current frequency components within a second frequency range higher than the first frequency range to the reference voltage, the first frequency being in the second frequency range and the first portion being larger than the second portion; and

coupling the bias current to the gain stage to produce a mixer output.

24. The method of claim 23 wherein the first frequency is an RF frequency.

25. The method of claim 23 wherein the second portion of the bias current frequency components is substantially zero at the first frequency.

26. The method of claim 23 wherein the mixer output is proportional to the product of the first signal and the second signal.