Acquisition system for a multi-channel relatively long record length digital storage oscilloscope

• US 6,748,335 B2
• Filed: 05/06/2002
• Issued: 06/08/2004
• Est. Priority Date: 05/06/2002
• Status: Expired due to Fees

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Pickerd, John J.
• Primary Examiner(s): Shah, Kamini
• Assistant Examiner(s): Pretlow, Demetrius R.
• Application Number:
  US10/140,790
• Publication Number:
  US 20030208328A1
• Time in Patent Office: 764 Days
• Field of Search: 702/66-69, 702/127, 345/440.1
• US Class Current: 702/66
• CPC Class Codes: G01R 13/0254 for triggering, synchronisation
• CPC Class Codes: G01R 13/029 Software therefor
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers

Abstract

A real time multi-channel digital storage oscilloscope acquires a relatively long data record for each channel in an acquisition memory and processes the data of the relatively long data record to search for predetermined events. Upon detection of such a predetermined event, circuitry generates an event detect signal, and data comprising an acquisition frame surrounding the event is applied to a waveform processing and display system. The relatively long data record can be replayed in order to perform additional searches throughout the data record using different search criteria, thereby permitting multiple waveforms to be displayed simultaneously, each being captured as a result of a different user-defined event. A screen display may be programmed to display a different kind of event such as Runt signal, Overshoot, or Pulsewidth Violation in each waveform, or to display multiple occurrences of the same kind of event such as Runt signal in each waveform. The multiple waveforms of the screen display may be derived from a single channel or from different channels.

Claims

1. An acquisition system for a multi-channel long record length digital oscilloscope, comprising:

a plurality of input terminals for receiving signals under test;

an analog-to-digital converter having an input coupled to said input terminals for receiving said signals under test, and producing digital samples of said signals under test at an output;

a trigger circuit having an input coupled to said input terminals for receiving said signals under test, and producing a trigger signal at an output in response to detection of a predetermined trigger event in one of said signals under test;

deep acquisition memory for storing said digital samples of said signals under test as a plurality of relatively long length data records that form a long length data record as a function of the trigger signal; and

processor circuitry for examining said stored digital samples from the long length data record in a post acquisition mode of operation and producing an event detect signal in response to detection of a predetermined secondary event in said stored digital samples, and causing a predetermined amount of said stored digital samples to be read from said acquisition memory for processing and display;

said predetermined amount of said stored digital samples being less than any one of the relatively long length data records and being related in time to said event detect signal.

2. The acquisition system of claim 1 wherein:

said processor operates in one of a one-shot mode and an Autorun mode;

in said one-shot mode said processor circuitry repeatedly examines said long length data record; and

in said Autorun mode upon completion of examination of said long length data record said processor circuitry causes the acquisition of new digital samples from said signals under test as the long length data record.

3. The acquisition system of claim 2 wherein:

data representative of said predetermined secondary event is input to said processor circuitry by a user for causing said processor circuitry to produce said event detect signal upon detection of said predetermined secondary event.

4. The acquisition system of claim 3 wherein:

said processor circuitry is responsive to input data entered by a user for changing said data representative of said predetermined secondary event;

said input data entered by said user is accepted by said processor circuitry before or during said examination of said long length data record.

5. The acquisition system of claim 4 wherein:

said predetermined amount of stored digital samples represents a frame of samples surrounding said predetermined secondary event, and a magnitude of said frame is controllable by said user.

6. The acquisition system of claim 5 wherein said oscilloscope has multiple channels:

each of said channels having an acquisition memory associated therewith;

each of said acquisition memories being concatenated with the others to form said deep acquisition memory.

7. The acquisition system of claim 6 wherein

said processor circuitry comprises individual processing units each of which is associated with a respective one of said acquisition memories of said channels.

8. The acquisition system of claim 7 wherein:

each of said individual processing units can be programmed to detect a plurality of different predetermined secondary events; and

waveforms representative of data surrounding each of said different predetermined secondary events are simultaneously displayed on a display screen of said oscilloscope.

9. The acquisition system of claim 6 wherein said processor circuitry is an FPGA.

10. The acquisition system of claim 6 wherein said processor circuitry Is a microcomputer.

11. The acquisition system of claim 6 wherein said processor circuitry is an ASIC.

12. The acquisition system of claim 7 wherein said individual processing units are FPGAs.

13. The acquisition system of claim 7 wherein said individual processing units are microcomputers.

14. The acquisition system of claim 7 wherein said individual processing units are ASICs.

15. A long record length digital oscilloscope, comprising:

a plurality of input terminals for receiving signals under test;

an analog-to-digital converter having an input coupled to said input terminals for receiving said signals under test, and producing digital samples of said signals under test at an output;

a trigger circuit having an input coupled to said input terminals for receiving said signals under test, and producing a trigger signal at an output in response to detection of a predetermined trigger event in one of said signals under test;

a deep acquisition memory for storing said digital samples of said signals under test as a plurality of relatively long length data records that form a long length data record;

a demultiplexer unit coupled between said analog-to-digital converter and said deep acquisition memory for receiving said digital samples and controlling the flow of said samples to said deep acquisition memory in response to said trigger signal;

processor circuitry for examining said stored digital samples from said long length data record in a post acquisition mode of operation and producing an event detect signal in response to detection of a predetermined secondary event in said long length data record; and

a system processor for causing a predetermined amount of said stored digital samples to be read from said deep acquisition memory for processing and display in response to said event detect signal;

said predetermined amount of said stored digital samples being less than one of the relatively long length data records and being related in time to said event detect signal.

16. The long record length digital oscilloscope of claim 15 wherein:

said system processor operates in one of a one-shot mode and an Autorun mode;

in said one-shot mode said system processor repeatedly examines said long length data record;

in said Autorun mode, upon completion of examination of said long length data record, said system processor causes the acquisition of new digital samples from said signals under test as said relatively long length data records.

17. The long record length digital oscilloscope of claim 16 wherein:

data representative of said predetermined secondary event is input to said system processor by a user for causing said system processor to produce said event detect signal upon detection of said predetermined secondary event.

18. The long record length digital oscilloscope of claim 17 wherein:

said system processor is responsive to input by a user for changing said data representative of said predetermined secondary event;

said input by said user is accepted by said system processor before or during said examination of said long length data record.

19. The long record length digital oscilloscope of claim 18 wherein:

said predetermined amount of stored digital samples represents a frame of samples surrounding said predetermined secondary event, and a magnitude of said frame is controllable by said user.

20. The long record length digital oscilloscope of claim 19 wherein:

said system processor can be programmed to detect a plurality of different predetermined secondary events; and

waveforms representative of data surrounding each of said different predetermined secondary events are simultaneously displayed on a display screen of said oscilloscope.

21. The long record length digital oscilloscope of claim 20 wherein said system processor is an FPGA.

22. The long record length digital oscilloscope of claim 20 wherein said system processor is a microcomputer.

23. The long record length digital oscilloscope of claim 20 wherein said system processor is an ASIC.

24. A digital storage oscilloscope, comprising:

a plurality of input terminals for receiving signals under test;

an analog-to-digital converter having an input coupled to said input terminals for receiving said signals under test, and producing digital samples of said signals under test at an output;

a trigger circuit having an input coupled to said input terminals for receiving said signals under test, and producing a trigger signal at an output in response to detection of a predetermined trigger event in one of said signals under test;

a deep acquisition memory for storing said digital samples of said signals under test as a plurality of relatively long data records that form a long length data record;

a demultiplexer unit coupled between said analog-to-digital converter and said deep acquisition memory for receiving said digital samples and controlling the flow of said samples to said deep acquisition memory in response to said trigger signal; and

a system processor for examining said stored digital samples from said long length data record in a post acquisition mode of operation for detecting a predetermined secondary event in said stored digital samples;

said system processor causing a predetermined amount of said stored digital samples to be read from said deep acquisition memory for processing and display in response to said detection of said predetermined secondary event;

said predetermined amount of said stored digital samples being less than one of said relatively long length data records and being related in time to said event detect signal.

25. The digital storage oscilloscope of claim 24 wherein said oscilloscope has multiple channels:

each of said channels having an acquisition memory associated therewith;

said system processor being capable of being programmed to detect a plurality of predetermined secondary events in said acquisition memories; and

waveforms representative of data surrounding each of said predetermined secondary events are simultaneously displayed on a display screen of said oscilloscope.

26. The long record length digital oscilloscope of claim 25 wherein said system processor is an FPGA.

27. The long record length digital oscilloscope of claim 25 wherein said system processor is a microcomputer.

28. The long record length digital oscilloscope of claim 25 wherein said system processor is an ASIC.

29. A method for use in an oscilloscope for displaying a waveform of interest comprising the steps of:

acquiring data from a plurality of signals under test to form a plurality of relatively long length data records that form a long length data record in a deep acquisition memory in response to a trigger signal;

examining the long length data record in a post processing mode of operation for the occurrence of a user-defined secondary event;

upon detection of said user-defined secondary event, applying data comprising an acquisition frame surrounding the said user-defined secondary event to a waveform processing and display system.

30. The method of claim 29 wherein:

said relatively long length data records are replayed to perform said examining and said applying steps throughout the relatively long length data records using different predetermined search criteria defining different user-defined secondary events; and

wherein

said applying step causes multiple ones of said waveforms of interest to be displayed simultaneously, each being captured as a result of a different one of said user-defined secondary events.

31. The method of claim 29 wherein

said relatively long length data records are replayed to perform said examining and said applying steps throughout said relative long length data records using a single search criterion for said user-defined secondary event;

and wherein

said applying step causes multiple ones of said waveforms of interest to be displayed simultaneously, each being captured as a result of said user-defined secondary event.