Semiconductor non-volatile memory device having an improved write speed

• US 6,750,102 B1
• Filed: 10/12/2000
• Issued: 06/15/2004
• Est. Priority Date: 05/20/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Lancaster, Loren T.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): BROPHY, JAMIE LYNN
• Application Number:
  US09/689,442
• Time in Patent Office: 1,342 Days
• Field of Search: 438/237, 438/197, 438/292, 438/299, 438/301, 438/585, 438/216, 438/257, 438/261, 438/264, 438/287, 438/288, 438/541, 438/593, 257/261, 257/314, 257/315, 257/317, 257/321
• US Class Current: 438/261
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

A non-volatile memory IGFET device has a gate dielectric stack that is di lectrically equivalent to a layer of silicon dioxide having a thickness of to 170 Å or less. Above the dielectric stack is a polycrystalline silicon gate that is doped in an opposite manner to that of the source and drain regions of the transistor. By using a gate doping that is opposite to that of the IGFET source and drain regions the poly depletion layer that can occur during programming in modern and advanced memory devices is eliminated according to this invention. The device of this invention forms an accumulation layer in the poly rather than a depletion layer. This difference not only greatly improves the program speed, but allows for selecting the gate doping at levels as low as 10¹¹/cm³, or less, without significantly compromising the program speed. Further, since the majority of the applied voltage in a device according to this invention is dropped over the gate dielectric, rather than shared between the gate dielectric and a depletion layer in the gate poly, the device of this invention can be scaled in gate dielectric thickness without significantly compromising the program speed.

Claims

1. A method for making a non-volatile semiconductor device comprising:

forming a multilayer gate dielectric having a charge storage layer and being dielectrically equivalent to a layer of silicon dioxide having a thickness that is less than 200 angstroms;

forming a control gate comprising polycrystalline silicon of a first conductivity type on said gate dielectric; and

forming source and drain regions separated by a channel region in a semiconductor substrate, said source and drain regions having a second conductivity type different from said first conductivity type.

2. The method of claim 1, wherein:

forming the multilayer gate dielectric includes forming a bottom dielectric, the charge storage layer over the bottom dielectric, and a top dielectric over the charge storage layer.

3. The method of claim 2, wherein:

forming the bottom dielectric includes forming a layer of silicon dioxide.

4. The method of claim 2, wherein:

forming the bottom dielectric includes thermally growing a layer of silicon dioxide.

5. The method of claim 2, wherein:

forming the charge storage layer includes forming a layer selected from the group consisting of silicon nitride, silicon oxynitride, silicon-rich silicon dioxide, and a ferroelectric material.

6. The method of claim 2, wherein:

forming the top dielectric includes forming a layer of silicon dioxide.

7. The method of claim 6, wherein:

forming the top dielectric includes thermally growing the layer of silicon dioxide.

8. The method of claim 6, wherein:

forming the top dielectric includes depositing the layer of silicon dioxide.

9. The method of claim 1, wherein:

forming the control gate includes forming a polycrystalline silicon gate doped to an n-type conductivity; and

the source and drain regions have a p-type conductivity.

10. The method of claim 1, wherein:

forming the control gate includes forming a polycrystalline silicon gate doped to a p-type conductivity; and

the source and drain regions have an n-type conductivity.

11. The method of claim 1, wherein:

forming the control gate includes forming a polycrystalline silicon gate having a dopant concentration greater than about 10¹⁰ atoms/cm³.