Methods for sputter deposition of high-k dielectric films

• US 6,750,126 B1
• Filed: 01/08/2003
• Issued: 06/15/2004
• Est. Priority Date: 01/08/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chambers, James Joseph, Rotondaro, Antonio Luis Pacheco, Visokay, Mark, Colombo, Luigi
• Primary Examiner(s): THOMPSON, CRAIG
• Application Number:
  US10/338,276
• Time in Patent Office: 524 Days
• Field of Search: 438/585, 438/785, 438/243, 438/386
• US Class Current: 438/585
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/314 Inorganic layers H01L21/3105, H01L21/32 take precedence
• CPC Class Codes: H01L 21/3143 composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Methods are disclosed for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition, in which nitridation and/or oxidation or other adverse reaction of the semiconductor material is reduced or minimized by reducing the bombardment of the semiconductor body by positively charged reactive ions such as oxygen ions or nitrogen ions during the sputter deposition process. The sputtering operation may be a two-step process in which ionic bombardment of the semiconductor material is minimized in an initial deposition step to form a first layer portion covering the semiconductor body, and the second step completes the desired high-k dielectric layer. Mitigation of unwanted nitridation and/or oxidation or other adverse reaction is achieved through one, some, or all of high sputtering deposition pressure, repulsive wafer biasing, increased wafer-plasma spacing, low partial pressures for reactant gases, and low sputtering powers or power densities.

Claims

1. A method of fabricating a transistor gate structure, comprising:

performing a sputter deposition process to form a high-k dielectric layer over a semiconductor body in a wafer, the high-k dielectric layer comprising a high-k oxide, an oxynitride, or a nitride;

minimizing bombardment of the semiconductor body by positively charged reactive ions during the sputter deposition process;

forming a gate electrode layer over the high-k dielectric layer; and

patterning the gate electrode layer and the high-k dielectric layer.

2. The method of claim 1, wherein performing the sputter deposition process comprises controlling a chamber pressure of a sputtering chamber and wherein minimizing bombardment of the semiconductor body comprises controlling the chamber pressure to be about 10 mTorr or more and about 100 mTorr or less.

3. The method of claim 2, wherein minimizing bombardment of the semiconductor body comprises controlling the chamber pressure to be about 30 mTorr or less.

4. The method of claim 1, wherein performing the sputter deposition process comprises biasing the wafer with respect to a plasma potential and wherein minimizing bombardment of the semiconductor body comprises biasing the wafer positive with respect to the plasma potential to repel or retard the kinetic energy of positively charged reactive ions during the sputter deposition process.

5. The method of claim 4, wherein biasing the wafer positive with respect to the plasma potential comprises controlling a potential of the wafer with respect to a sputter deposition system ground.

6. The method of claim 4, wherein minimizing bombardment of the semiconductor body comprises minimizing bombardment by positively charged oxygen or nitrogen ions during the sputter deposition process.

7. The method of claim 1, wherein performing the sputter deposition process comprises locating the wafer in a sputtering chamber and wherein minimizing bombardment of the semiconductor body comprises spacing the wafer from a plasma in the sputtering chamber by a sufficient distance to reduce the energy of positively charged reactive ions hitting the wafer during the sputter deposition process.

8. The method of claim 7, wherein spacing the wafer from the plasma comprises locating the wafer about 100 mm or more away from a target in the sputtering chamber.

9. The method of claim 7, wherein minimizing bombardment of the semiconductor body comprises minimizing bombardment by positively charged oxygen or nitrogen ions during the sputter deposition process.

10. The method of claim 1, wherein performing the sputter deposition process comprises providing at least one reactant gas to a sputtering chamber, the at least one reactant gas being oxygen or nitrogen, and wherein minimizing bombardment of the semiconductor body comprises controlling a pressure of the at least one reactant gas to reduce the amount of positively charged oxygen ions or nitrogen ions hitting the wafer during the sputter deposition process.

11. The method of claim 10, wherein minimizing bombardment of the semiconductor body comprises controlling a pressure of the at least one reactant gas to about 0.1 mTorr or less during the sputter deposition process.

12. The method of claim 11, wherein minimizing bombardment of the semiconductor body comprises controlling a pressure of the at least one reactant gas to about 0.01 mTorr or less during the sputter deposition process.

13. The method of claim 12, wherein the at least one reactant gas is oxygen.

14. The method of claim 12, wherein the at least one reactant gas is nitrogen.

15. The method of claim 1, wherein performing the sputter deposition process comprises controlling a sputtering power density level and wherein minimizing bombardment of the semiconductor body comprises controlling the sputtering power density level to about 0.11 W/cm² or less.

16. The method of claim 15, wherein minimizing bombardment of the semiconductor body comprises controlling the sputtering power density level to 0.01 W/cm² or less.

17. The method of claim 1, wherein performing the sputter deposition process comprises:

depositing a first portion of the high-k dielectric layer covering the semiconductor body by sputter deposition; and

depositing a second portion of the high-k dielectric layer over the first portion by sputter deposition;

wherein minimizing bombardment of the semiconductor body comprises minimizing bombardment of the semiconductor body by positively charged reactive ions while depositing the first portion of the high-k dielectric layer.

18. The method of claim 17, wherein minimizing bombardment of the semiconductor body comprises minimizing bombardment by positively charged oxygen or nitrogen ions while depositing the first portion of the high-k dielectric layer.

19. A method of forming a transistor gate, comprising:

depositing a first portion of a high-k dielectric layer over a semiconductor body in a wafer by sputter deposition using a first sputter deposition process, the first portion of the high-k dielectric layer comprising a high-k oxide, an oxynitride, or a nitride;

minimizing adverse reaction of the semiconductor body during the first sputter deposition process;

depositing a second portion of the high-k dielectric layer over the first portion by sputter deposition using a second sputter deposition process, the second portion of the high-k dielectric layer comprising a high-k oxide, an oxynitride, or a nitride;

forming a gate electrode layer over the second portion of the high-k dielectric layer; and

patterning the gate electrode layer and the high-k dielectric layer.

20. The method of claim 19, wherein depositing the first portion of a high-k dielectric layer comprises controlling a chamber pressure of a sputtering chamber and wherein minimizing adverse reaction of the semiconductor body comprises controlling the chamber pressure to be about 10 mTorr or more and about 100 mTorr or less.

21. The method of claim 20, wherein minimizing adverse reaction of the semiconductor body comprises controlling the chamber pressure to be about 30 mTorr or less.

22. The method of claim 19, wherein depositing the first portion of a high-k dielectric layer comprises biasing the wafer with respect to a plasma potential and wherein minimizing adverse reaction of the semiconductor body comprises biasing the wafer positive with respect to the plasma potential to repel or retard the kinetic energy of positively charged reactive ions during the sputter deposition process.

23. The method of claim 22, wherein biasing the wafer positive with respect to the plasma potential comprises controlling a potential of the wafer with respect to a sputter deposition system ground.

24. The method of claim 22, wherein minimizing adverse reaction of the semiconductor body comprises minimizing oxidation or nitridation during the sputter deposition process.

25. The method of claim 19, wherein depositing the first portion of a high-k dielectric layer comprises locating the wafer in a sputtering chamber and wherein minimizing adverse reaction of the semiconductor body comprises spacing the wafer from a plasma in the sputtering chamber by a sufficient distance to reduce the energy of positively charged reactive ions hitting the wafer during the sputter deposition process.

26. The method of claim 25, wherein spacing the wafer from the plasma comprises locating the wafer about 100 mm or more away from a target in the sputtering chamber.

27. The method of claim 25, wherein minimizing adverse reaction of the semiconductor body comprises minimizing oxidation or nitridation during the sputter deposition process.

28. The method of claim 19, wherein depositing the first portion of a high-k dielectric layer comprises providing at least one reactant gas to a sputtering chamber, the at least one reactant gas being oxygen or nitrogen, and wherein minimizing adverse reaction of the semiconductor body comprises controlling a pressure of the at least one reactant gas to reduce the amount of positively charged reactive ions hitting the wafer during the sputter deposition process.

29. The method of claim 28, wherein minimizing adverse reaction of the semiconductor body comprises controlling a pressure of the at least one reactant gas to about 0.1 mTorr or less during the sputter deposition process.

30. The method of claim 29, wherein minimizing adverse reaction of the semiconductor body comprises controlling a pressure of the at least one reactant gas to about 0.01 mTorr or less during the sputter deposition process.

31. The method of claim 30, wherein the at least one reactant gas is oxygen.

32. The method of claim 30, wherein the at least one reactant gas is nitrogen.

33. The method of claim 19, wherein depositing the first portion of a high-k dielectric layer comprises controlling a sputtering power density level and wherein minimizing adverse reaction of the semiconductor body comprises controlling the sputtering power density level to about 0.11 W/cm² or less.

34. The method of claim 33, wherein minimizing adverse reaction of the semiconductor body comprises controlling the sputtering power density level to 0.01 W/cm² or less.

35. The method of claim 19, wherein minimizing adverse reaction of the semiconductor body comprises minimizing oxidation or nitridation during the sputter deposition process.

36. A method of forming a high-k dielectric layer over a semiconductor body during fabrication of a transistor gate, the method comprising:

performing a sputter deposition process to form a high-k dielectric layer over a semiconductor body in a wafer, the high-k dielectric layer comprising a high-k oxide, an oxynitride, or a nitride; and

minimizing adverse reaction of the semiconductor body during the sputter deposition process.

37. The method of claim 36, wherein minimizing adverse reaction of the semiconductor body comprises minimizing bombardment of the semiconductor body by positively charged oxygen ions or nitrogen ions during the sputter deposition process.

38. The method of claim 36, wherein performing the sputter deposition process comprises:

depositing a first portion of the high-k dielectric layer covering the semiconductor body by sputter deposition; and

depositing a second portion of the high-k dielectric layer over the first portion by sputter deposition;

wherein minimizing adverse reaction of the semiconductor body comprises minimizing oxidation or nitridation of the semiconductor body while depositing the first portion of the high-k dielectric layer.

39. The method of claim 38, wherein minimizing adverse reaction of the semiconductor body comprises minimizing bombardment of the semiconductor body by positively charged oxygen ions or nitrogen ions during the sputter deposition process.

40. The method of claim 36, wherein performing the sputter deposition process comprises controlling a chamber pressure of a sputtering chamber and wherein minimizing adverse reaction of the semiconductor body comprises controlling the chamber pressure to be about 10 mTorr or more and about 100 mTorr or less.

41. The method of claim 40, wherein minimizing adverse reaction of the semiconductor body comprises controlling the chamber pressure to be about 30 mTorr or less.

42. The method of claim 40, wherein performing the sputter deposition process comprises biasing the wafer with respect to a plasma potential and wherein minimizing adverse reaction of the semiconductor body comprises biasing the wafer positive with respect to the plasma potential to repel or retard the kinetic energy of positively charged reactive ions during the sputter deposition process.

43. The method of claim 42, wherein biasing the wafer positive with respect to the plasma potential comprises controlling a potential of the wafer with respect to a sputter deposition system ground.

44. The method of claim 40, wherein performing the sputter deposition process comprises locating the wafer in a sputtering chamber and wherein minimizing adverse reaction of the semiconductor body comprises spacing the wafer from a plasma in the sputtering chamber by a sufficient distance to reduce the energy of positively charged reactive ions hitting the wafer during the sputter deposition process.

45. The method of claim 44, wherein spacing the wafer from the plasma comprises locating the wafer about 100 mm or more away from a target in the sputtering chamber.

46. The method of claim 40, wherein performing the sputter deposition process comprises providing at least one reactant gas to a sputtering chamber, the at least one reactant gas being oxygen or nitrogen, and wherein minimizing adverse reaction of the semiconductor body comprises controlling a pressure of the at least one reactant gas to reduce the amount of positively charged oxygen ions or nitrogen ions hitting the wafer during the sputter deposition process.

47. The method of claim 46, wherein minimizing adverse reaction of the semiconductor body comprises controlling a pressure of the at least one reactant gas to about 0.1 mTorr or less during the sputter deposition process.

48. The method of claim 47, wherein minimizing adverse reaction of the semiconductor body comprises controlling a pressure of the at least one reactant gas to about 0.01 mTorr or less during the sputter deposition process.

49. The method of claim 48, wherein the at least one reactant gas is oxygen.

50. The method of claim 48 wherein the at least one reactant gas is oxygen.

51. The method of claim 40, wherein performing the sputter deposition process comprises controlling a sputtering power density level and wherein minimizing adverse reaction of the semiconductor body comprises controlling the sputtering power density level to about 0.11 W/cm² or less.

52. The method of claim 51, wherein minimizing adverse reaction of the semiconductor body comprises controlling the sputtering power density level to 0.01 W/cm² or less.