Method and apparatus for electrically testing and characterizing formation of microelectric features

• US 6,750,152 B1
• Filed: 10/01/1999
• Issued: 06/15/2004
• Est. Priority Date: 10/01/1999
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Delphi Technologies, Inc. (Aptiv PLC)
• Inventors: Christenson, John Carl, Staller, Steven Edward, Healton, Robert Lawrence, Freeman, John Emmett, Chase, Troy Allan
• Primary Examiner(s): Powell, William A.
• Application Number:
  US09/411,339
• Time in Patent Office: 1,719 Days
• Field of Search: 216/2, 216/14, 216/59, 216/61, 216/84, 216/86, 438/8, 438/9, 438/14, 438/17, 438/689, 438/719, 438/753, 438/735, 438/743, 324/661, 324/676, 735/17.A, 735/17.R
• US Class Current: 438/735
• CPC Class Codes: B81C 99/004 during manufacturing
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A semiconductor wafer is etched to create an array of MEMS devices and at the same time, test sites having geometry which represent critical geometry of the MEMS devices. Probe contacts are provided in the test sites to permit measurement of resistance and capacitance between test site geometry as a way of determining the effectiveness of the etch. One test site comprises a ladder of semiconductor structures separated by gaps of graded width. Another test site comprises finger structures formed over a cavity and the probe contacts are located so as to detect inter-finger capacitance and resistance (or continuity) as well as intra-finger resistance.

Claims

1. A method of testing an array of electronic or mechanical devices which are batch-formed from an essentially continuous layer of semiconductor material to determine the effect of the batch forming medium on the physical and electrical properties of the devices formed thereby using test sites comprising the steps of:

a) forming electrical test probe contacts in said test sites;

b) discretizing the locations and geometry of said devices in said material layer;

wherein said geometry includes the definition of one or more gaps to be formed in said material layer which gaps affect the electrical properties of said devices;

c) discretizing one or more of said test sites in said material layer so as to define, after batch forming, at least one gap which is dimensionally representative of a gap in said device geometry;

d) subjecting the layer to the forming medium; and

e) measuring at least one electrical property associated with said test site gap via said probe contacts.

2. A method as defined in claim 1 wherein the discretizing steps include the application of a pattern of material to said semiconductor layer which is resistant to the forming medium.

3. A method as defined in claim 2 wherein said forming medium is an etchant.

4. A method as defined in claim 3 wherein said etchant is a deep reactive ion enchant.

5. A method as defined in claim 1 wherein steps (a), (b), and (c) are performed in any order before step (d).

6. A method as defined in claim 1 wherein the test probe contacts are formed on opposite sides of a test site gap.

7. A method as defined in claim 1 wherein the geometry of a device and a test site after step (d) is such as to define an elongate area of semiconductor material defined by lateral gaps in said semiconductor material as wherein the step of forming test probe contacts includes the formation of test probe contacts at spaced apart locations along said elongate area.

8. A method of batch etching an array of electronic or mechanical devices from an essentially continuous layer of semiconductor materials and, contemporaneously with said etching method, conducting a test to determine the effects of the etchant on the electrical properties of the devices using test sites comprising the steps of:

a) forming electrical test probe contacts in said test site;

b) defining the locations and geometry of said devices in said semiconductor material layer by the application of an etchant resistant material to a surface of said semiconductor layer wherein the geometry includes the definition of gaps in said material layer to be formed by the etchant and which affect the electrical, mechanical, or both the electrical and the mechanical properties of said devices;

c) defining one or more of said test sites in said semiconductor material layer by the application of etchant resistant material so as to define a plurality of graded gaps dimensionally representative of the gaps in a device geometry;

d) subjecting the semiconductor layer to the etchant to simultaneously form said device gaps and said test site gaps with said test site gaps interleaved with said test probe contacts; and

e) measuring at least one electrical property associated with said test site gaps.

9. A method as defined in claim 8 wherein steps (a), (b), and (c) are performed in any order before step (d).

10. A method as defined in claim 8 wherein said electrical property is capacitance.

11. A method as defined in claim 8 wherein said electrical property is resistance or electrical continuity.

12. A method as defined in claim 8 wherein the geometry of a device is such as to include a plurality of elongate semiconductor finger portions separated by gaps and the geometry of said test site includes the formation of a plurality of elongate semiconductor fingers separated by gaps, and the step of defining test probe contacts includes the definition of contacts at the terminal portions of individual fingers, and the step of measuring includes the measurement of at least one of the following:

(i) the capacitance across said gaps;

(ii) the resistance along said elongate fingers;

(iii) the resistance across said gaps; and

(iv) the electrical continuity across said gaps.

13. In a layer of etched semiconductor material allocated primarily to the formation of semiconductor devices having a geometry which includes at least one capacitive gap of interest:

a test site formed in said semiconductor layer simultaneously with said devices and comprising at least two volumes of semiconductor material isolated from the layer by an isolation trench and from one another by a trench representative of the capacitive gap of interest;

said structure further comprising electrical contact means on said semiconductor structures for permitting the capacitance in the gap of interest to be measured after the etch treatment.

14. In a layer of etched semiconductor material allocated primarily to the formation of semiconductor devices having a geometry which includes at least one capacitive gap of interest:

a test site formed in said semiconductor layer simultaneously with said devices and comprising at least two volumes of semiconductor material isolated from the layer by an isolation trench and from one another by a trench representative of the capacitive gap of interest;

said structure further comprising electrical contact means on said semiconductor structures for permitting the resistance between said two volumes of semiconductor material to be measured as said gap of interest is formed.

15. In an etched semiconductor layer devoted primarily to the formation of semiconductor devices having structures separated from one another by etched trenches:

a test site formed in said layer and having at least one structure representative of the structures in the semiconductor devices;

said structure in said test site being isolated from the remainder of said seimconductor layer by an isolation trench;

said structure in said test site further having electrical probe contacts associated with the distal ends thereof to permit the measurement of the electrical resistance thereof.

16. An apparatus as defined in claim 15 wherein the finger-like semiconductor structure is formed in part over a cavity.