Super-self-aligned trench-gated DMOS with reduced on-resistance

• US 6,750,507 B2
• Filed: 05/14/2002
• Issued: 06/15/2004
• Est. Priority Date: 04/22/1999
• Status: Expired due to Term

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Grabowski, Wayne
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Malsawma, Lex H.
• Application Number:
  US10/146,668
• Publication Number:
  US 20020195657A1
• Time in Patent Office: 763 Days
• Field of Search: 257/302, 257/328, 257/330, 257/396, 438/212, 438/268, 438/270, 438/272, 438/430, 438/431
• US Class Current: 257/328
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Claims

1. A trench-gated power MOSFET comprising:

a semiconductor body having a trench formed therein, a wall of the trench intersecting a major surface of the semiconductor body at a trench corner, the semiconductor body comprising;

a source region of a first conductivity type adjacent the trench and the major surface of the body;

a body region of a second conductivity type forming a junction with the source region, the body region including a channel region adjacent the wall of the trench; and

a drain region of the first conductivity type forming a junction with the body region; and

a gate disposed in the trench, the gate being bordered by gate oxide, the gate oxide comprising a first portion adjacent the channel region, a second portion overlying the gate, and a third portion adjacent a bottom of the trench, wherein the second portion is thicker than the first portion and has an upper surface above a level of the major surface of the semiconductor body, and wherein the third portion is thicker than the first portion and an upper surface of the third portion is at a level with the junction between the body region and the drain region; and

a metal layer in contact with the major surface of the semiconductor body, the contact between the metal layer and the major surface extending laterally to the trench corner.

2. The trench-gated power MOSFET of claim 1, wherein a lower surface of the second portion of the gate oxide is below the level of the major surface of the semiconductor body.

3. The trench-gated power MOSFET of claim 1, wherein the metal layer extends from the major surface of the semiconductor body onto the upper surface of the second portion of the gate oxide.

4. A trench-gated power MOSFET comprising:

a semiconductor body having a trench formed in a major surface of the semiconductor body, the semiconductor body comprising;

a source region of a first conductivity type adjacent the trench and the major surface of the body;

a body region of a second conductivity type forming a junction with the source region, the body region comprising a channel region adjacent the wall of the trench; and

a drain region of the first conductivity type forming a junction with the body region; and

a gate disposed in the trench, the gate being bordered by gate oxide, the gate oxide comprising a first portion adjacent the channel region, a second portion overlying the gate, and a third portion adjacent a bottom of the trench, wherein the second portion is thicker than the first portion, does not overlap the major surface of the semiconductor body outside the trench, and has an upper surface that is above a level of the major surface of the semiconductor body, and wherein the third portion is thicker than the first portion and an upper surface of the third portion is at a level with the junction between the body region and the drain region; and

a metal layer in contact with the major surface of the semiconductor body.

5. The trench-gated power MOSFET of claim 4, wherein a lower surface of the second portion of the gate oxide is below the level of the major surface of the semiconductor body.

6. The trench-gated power MOSFET of claim 4, wherein the metal layer extends from the major surface of the semiconductor body onto the upper surface of the second portion of the gate oxide.

7. A trench-gated power MOSFET comprising;

a semiconductor body having a trench formed in a major surface of the semiconductor body, the semiconductor body comprising;

a source region of a first conductivity type adjacent the trench and the major surface of the body;

a body region of a second conductivity type forming a junction with the source region, the body region comprising a channel region adjacent the wall of the trench; and

a drain region of the first conductivity type forming a junction with the body region; and

a gate disposed in the trench, the gate being bordered by gate oxide, the gate oxide comprising a first portion adjacent the channel region and a second portion at a bottom of the trench, the second portion being thicker than the first portion, wherein an upper surface of the second portion is at a level with the junction between the body region and the drain region.

8. The trench-gated power MOSFET of claim 7, wherein the gate oxide further comprises a third portion overlying the gate.

9. The trench-gated power MOSFET of claim 8, further comprising a metal layer on the major surface of the semiconductor body and extending onto the third portion of the gate oxide, wherein the metal layer makes electrical contact with the source region and is isolated from the gate by the third portion of the gate oxide.