Power semiconductor switching element provided with buried electrode

• US 6,750,508 B2
• Filed: 06/28/2001
• Issued: 06/15/2004
• Est. Priority Date: 06/30/2000
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tokano, Kenichi, Saito, Yoshihiko, Omura, Ichiro, Ohashi, Hiromichi, Saito, Wataru, Ogura, Tsuneo
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US09/892,545
• Publication Number:
  US 20020030237A1
• Time in Patent Office: 1,083 Days
• Field of Search: 257/329, 257/330, 257/331, 257/341, 257/397, 257/332
• US Class Current: 257/329
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 29/8725 : of the trench MOS barrier type [TMBS]

Abstract

A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Claims

1. A semiconductor element comprising:

a semiconductor substrate of a first conductivity type having a first major surface and a second major surface opposing the first major surface;

a drift layer of the first conductivity type formed on the first major surface of said semiconductor substrate;

a well layer of a second conductivity type selectively formed in a surface of said drift layer;

a source layer of the first conductivity type selectively formed in a surface of said well layer;

a trench formed to reach at least an inside of said drift layer from a surface of said source layer through said well layer;

a buried electrode having a first portion and a second portion being continuous to the first portion, the first portion being formed through a first insulating film in a region extending from the trench of said drift layer to a bottom surface of said trench, the second portion being led out from the first portion to an outside of a terminal portion;

a control electrode formed in a region extending from said source layer to said drift layer through said well layer in said trench to be insulated from said buried electrode through a second insulating film;

a first main electrode formed on the second major surface of said semiconductor substrate; and

a second main electrode connected to said source layer and said well layer.

2. An element according to claim 1, wherein said first insulating film has a thickness larger than a value obtained by multiplying a static breakdown voltage of said element by 20 Å

.

3. An element according to claim 1, wherein the first insulating film is thicker than the second insulating film.

4. An element according to claim 1, wherein an impurity concentration of said drift layer gradually increases toward said semiconductor substrate.

5. An element according to claim 1, wherein an impurity concentration of said drift layer is high near a side wall of said trench.

6. An element according to claim 1, wherein said trench takes the form of a stripe.

7. An element according to claim 1, wherein said buried electrode is electrically connected to said first or second main electrode.

8. An element according to claim 1, wherein said buried electrode is formed by burying a semi-insulating film in said trench through the first insulating film.

9. An element according to claim 1, wherein said buried electrode set in a floating state.

10. An element according to claim 1, wherein the trench has one of a circular horizontal cross section, a square horizontal cross section and a regular hexagonal horizontal cross section.

11. A semiconductor element comprising:

a semiconductor substrate of a first conductivity type having a first major surface and a second major surface opposing the first major surface;

a drift layer of the first conductivity type formed on the first major surface of said semiconductor substrate;

a well layer of a second conductivity type selectively formed in a surface of said drift layer;

a source layer of the first conductivity type selectively formed in a surface of said well layer;

a trench formed to reach at least an inside of said drift layer from a surface of said source layer through said well layer, the trench having one of a circular horizontal cross section, a square horizontal cross section and a regular hexagonal horizontal cross section;

a buried electrode formed through a first insulating film in a region extending from the trench of said drift layer to a bottom surface of said trench;

a control electrode formed in a region extending from said source layer to said drift layer through said well layer in said trench to be insulated from said buried electrode through a second insulating film;

a first main electrode formed on the second major surface of said semiconductor substrate; and

a second main electrode connected to said source layer and said well layer, wherein said first insulating film has a thickness which increases gradually toward said semiconductor substrate.