Device layout to improve ESD robustness in deep submicron CMOS technology

• US 6,750,517 B1
• Filed: 11/06/2000
• Issued: 06/15/2004
• Est. Priority Date: 11/06/2000
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ker, Ming-Dou, Wu, Mau-Lin
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US09/706,206
• Time in Patent Office: 1,317 Days
• Field of Search: 257/401, 257/355-363
• US Class Current: 257/401
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0277 involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A layout form ESD-protection MOS transistors include gate electrodes of the ESD-protection MOS transistors being formed with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity. The ESD protection transistors are NMOS and PMOS. The source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes. The wider ends of the gate electrodes straddle the peripheral boundaries of the active region. A modified layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner transistors.

Claims

1. A method of forming ESD-protection MOS transistors with an active region comprising:

forming gate electrodes of the ESD-protection MOS transistors with the gate electrodes being of uniform narrow width across the entire active region aside from the periphery thereof, and

forming gate electrodes with wider ends at the periphery of the active region,

whereby the transistors have improved turn-on uniformity.

2. The method of claim 1 wherein the ESD protection transistors are NMOS transistors and PMOS transistors.

3. The method of claim 1 wherein source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes at the periphery of the active region.

4. The method of claim 1 wherein the active region has peripheral boundaries, and the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.

5. The method of claim 1 including:

forming inner NMOS transistors and outer NMOS transistors and inner PMOS transistors and outer PMOS transistors in high-voltage-tolerant I/O circuits, and

forming the wider ends on only the inner NMOS transistors and the inner PMOS transistors.

6. A method of forming a layout for ESD-protection MOS transistors comprising:

forming gate electrodes of the ESD-protection MOS transistors with an active region having peripheral boundaries, and with the gate electrodes being of uniform narrow width in the active region aside from the periphery thereof, and

forming some of the gate electrodes with asymmetric wider ends at the periphery of the active region,

whereby the transistors have improved turn-on uniformity.

7. The method of claim 6 wherein the ESD protection transistors are NMOS transistors and PMOS transistors.

8. The method of claim 6 wherein source contacts and drain contacts for the transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes.

9. The method of claim 6 wherein the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.

10. The method of claim 6 wherein a modified layout style is provided for inner and outer NMOS transistors and PMOS transistors in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner NMOS transistors and PMOS transistors.

11. A layout form of ESD-protection MOS transistors comprising gate electrodes of the ESD-protection MOS transistors formed with the gate electrodes being of uniform narrow width in an active region thereof aside from the periphery thereof, and

some of the gate electrodes having wider ends at the periphery of the active region,

whereby the transistors have improved turn-on uniformity.

12. The layout of claim 11 wherein the ESD protection transistors are NMOS transistors and PMOS transistors.

13. The layout of claim 11 wherein source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes.

14. The layout of claim 11 wherein the active region has peripheral boundaries, and the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.

15. The layout of claim 11 wherein a modified layout style is provided for inner and outer NMOS transistors and PMOS transistors in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner NMOS transistors and PMOS transistors.

16. A layout form ESD-protection MOS transistors comprising:

gate electrodes of the ESD-protection MOS transistors formed with an active region having peripheral boundaries,

the gate electrodes being of uniformly narrow width in the active region aside from the periphery thereof, and

some of the gate electrodes having asymmetric wider ends at the periphery of the active region,

whereby the transistors have improved turn-on uniformity.

17. The layout of claim 16 wherein the ESD protection transistors are NMOS transistors and PMOS transistors.

18. The layout of claim 16 wherein source contacts and drain contacts for the transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes.

19. The layout of claim 16 wherein the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.

20. The layout of claim 16 wherein a modified layout style is provided for inner and outer NMOS transistors and PMOS transistors in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner NMOS transistors and PMOS transistors.

21. A layout form of ESD-protection MOS transistors comprising:

an active region with parallel rows of contacts including source contacts, the rows of source contacts and drain contacts for the transistors being located inboard of the periphery of the active region, with pairs of rows of drain contacts formed adjacent,

gate electrodes of the ESD-protection MOS transistors formed parallel with the rows of contacts with the gate electrodes being of uniformly narrow width in an active region thereof aside from the periphery thereof, and

some of the gate electrodes having wider ends at the periphery of the active region,

whereby the transistors have improved turn-on uniformity.

22. The layout of claim 21 wherein the gate electrode proximate to rows of source contacts have narrow ends at the periphery of the active region and the gate electrodes proximate to rows of drain contacts have widened ends at the periphery of the active region.

23. The layout of claim 21 wherein the gate electrode proximate to rows of source contacts have narrow ends at the periphery of the active region and the gate electrodes proximate to rows of drain contacts have widened ends at the periphery of the active region only on the sides proximate to the rows of drain contacts.