Multi-substrate microelectronic packages and methods for manufacture

• US 6,750,547 B2
• Filed: 12/26/2001
• Issued: 06/15/2004
• Est. Priority Date: 12/26/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeung, Boon Suan, Poo, Chia Yong, Waf, Low Siu
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/033,340
• Publication Number:
  US 20030116861A1
• Time in Patent Office: 902 Days
• Field of Search: 257/254, 257/179, 257/415, 257/777, 385/18, 427/96
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A microelectronic package and method for manufacture. The package can include first and second microelectronic substrates, each having a first surface with a connection site, and a second surface facing opposite the first surface. The second microelectronic substrate can be coupled to the first microelectronic substrate with the second surface of the second microelectronic substrate facing towards the first surface of the first microelectronic substrate. A conformal conductive link formed, for example, from sequentially deposited portions of conductive material, can be coupled between the first and second connection sites to provide for electrical communication between the substrates. Accordingly, the substrates can be stacked and electrically connected to reduce the footprint occupied by the substrates.

Claims

1. A microelectronic device package, comprising:

a first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;

a second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface, the second microelectronic substrate being coupled to the first microelectronic substrate to form a substrate assembly with the second surface of the second microelectronic substrate facing toward the first surface of the first microelectronic substrate; and

a conformal conductive link coupled between the first and second connection sites, the conductive link conforming at least generally to a contour of the substrate assembly immediately adjacent to the conformal conductive link.

2. The package of claim 1 wherein the first and second connection sites face in at least approximately the same direction.

3. The package of claim 1 wherein the conductive link conforms to a plane at least approximately parallel to the first surface of at least one of the first and second microelectronic substrates.

4. The package of claim 1, further comprising:

a first portion of dielectric material disposed on the first microelectronic substrate; and

a second portion of dielectric material disposed on the second microelectronic substrate, wherein the conductive material conforms to the first and second portions of dielectric material.

5. The package of claim 1, further comprising:

a first portion of dielectric material disposed on the first microelectronic substrate;

a second portion of dielectric material disposed on the second microelectronic substrate, wherein the conductive material conforms to the first and second portions of dielectric material;

a third portion of dielectric material disposed on the conductive material;

a third connection site coupled to the conductive material and the first and second connection sites; and

a volume of flowable conductive material disposed on the third connection site to provide electrical communication with the first and second microelectronic substrates.

6. The package of claim 1 wherein the first microelectronic substrate has an exposed edge between the first and second surfaces.

7. The package of claim 1, further comprising a dielectric material disposed on the first microelectronic substrate and wherein the conductive structure conforms to a contour of the dielectric material.

8. The package of claim 1 wherein the first microelectronic substrate has a first planform area in the plane of the second surface of the first microelectronic substrate and wherein the second microelectronic substrate has a second planform area in the plane of the second surface of the second microelectronic substrate, with the second planform area less than the first planform area.

9. The package of claim 1, further comprising a dielectric material disposed between the first surface of the first microelectronic substrate and the second surface of the second microelectronic substrate, the first and second microelectronic substrates being adhered to the dielectric material.

10. The package of claim 1, further comprising an intermediate structure connected between the first and second microelectronic substrates.

11. The package of claim 1, further comprising an adhesive film disposed between the first and second microelectronic substrates.

12. The package of claim 1 wherein the conductive link includes an elongated conductive structure that extends in three orthogonal directions between the first and second connection sites.

13. The package of claim 1 wherein the conductive link is non-self-supporting.

14. The package of claim 1 wherein the first microelectronic substrate includes an SRAM device and the second microelectronic substrate includes a flash memory device.

15. The package of claim 1 wherein the conductive link is a first conductive link, and wherein the package further comprises:

a third microelectronic substrate coupled to the second microelectronic substrate, the third microelectronic substrate having a first surface with a third connection site, the third microelectronic substrate further having a second surface facing opposite the first surface, the second surface of the third microelectronic substrate facing toward the first surface of second microelectronic substrate; and

sequentially disposed first and second portions of a second conductive link disposed on the substrate assembly and extending between the third connection site of the third microelectronic substrate and the second connection site of the second microelectronic substrate.

16. A microelectronic device package, comprising:

a first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;

a second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface, the second microelectronic substrate being coupled to the first microelectronic substrate with the second surface of the second microelectronic substrate facing toward the first surface of the first microelectronic substrate; and

a conductive link coupled between the first and second microelectronic substrates, the conductive link including a first portion of a conductive material disposed on at least one of the first and second connection sites, the conductive link further including a second portion of a conductive material sequentially disposed on the first portion to link the first connection site to the second connection site.

17. The package of claim 16 wherein the conductive link conforms to at least one of the first microelectronic substrate and a dielectric material disposed on the first microelectronic substrate.

18. The package of claim 16 wherein the conductive link conforms to a plane at least approximately parallel to the first surface of at least one of the first and second microelectronic substrates.

19. The package of claim 16, further comprising:

a first portion of dielectric material disposed on the first microelectronic substrate;

a second portion of dielectric material disposed on the second microelectronic substrate, wherein the conductive material conforms to the first and second portions of dielectric material;

a third portion of dielectric material disposed on the conductive material;

a third connection site coupled to the conductive material and the first and second connection sites; and

a volume of flowable conductive material disposed on the third connection site to provide electrical communication with the first and second microelectronic substrates.

20. The package of claim 16 wherein the first microelectronic substrate has an exposed edge between the first and second surfaces.

21. The package of claim 16, further comprising a dielectric material disposed between the first surface of the first microelectronic substrate and the second surface of the second microelectronic substrate, the first and second microelectronic substrates being adhered to the dielectric material.

22. The package of claim 16, further comprising an adhesive film disposed between the first and second microelectronic substrates.

23. The package of claim 16, wherein the conductive link includes an elongated conductive structure that extends in three orthogonal directions between the first and second connection sites.

24. The package of claim 16 wherein the conductive link is non-self-supporting.

25. A microelectronic device assembly, comprising:

a wafer having a plurality of non-singulated first microelectronic substrates, each first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;

a plurality of second microelectronic substrates each having a first surface with a second connection site and further having a second surface facing opposite the first surface, the second microelectronic substrates being coupled to the first microelectronic substrates while the first microelectronic substrates are non-singulated, and wherein the first surface of each first microelectronic substrate faces toward the second surface of a corresponding one of the plurality of second microelectronic substrates; and

a conductive link connected between the first and second connection sites.

26. The assembly of claim 25 wherein the conductive link conforms to a contour defined by the coupled first and second microelectronic substrates.

27. The assembly of claim 25 wherein the conductive link includes first and second sequentially deposited conductive portions.

28. The package of claim 25 wherein the first and second connection sites face in at least approximately the same direction.

29. The package of claim 25, further comprising:

a first portion of dielectric material disposed on the first microelectronic substrate;

a second portion of dielectric material disposed on the second microelectronic substrate, wherein the conductive material conforms to the first and second portions of the dielectric material;

a third portion of dielectric material disposed on the conductive material;

a third connection site coupled to the conductive material and the first and second connection sites; and

a volume of flowable conductive material disposed on the third connection site to provide electrical communication with the first and second microelectronic substrates.

30. The package of claim 25 wherein the first microelectronic substrate has an exposed edge between the first and second surfaces.

31. The package of claim 25, further comprising a dielectric material disposed between the first surface of the first microelectronic substrate and the second surface of the second microelectronic substrate, the first and second microelectronic substrates being adhered to the dielectric material.

32. The package of claim 25,further comprising an adhesive film disposed between the first and second microelectronic substrates.

33. The package of claim 25 wherein the conductive link includes an elongated conductive structure that extends in three orthogonal directions between the first and second connection sites.

34. The package of claim 25 wherein the conductive link is non-self-supporting.

35. A microelectronic device package, comprising:

a first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;

a second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface, the first microelectronic substrate being attached to the second microelectronic substrate with the first surface of the first microelectronic substrate facing the second surface of the second microelectronic substrate and the first and second connection sites facing in at least approximately the same direction to define a microelectronic device assembly, wherein a planform area of the assembly in a plane generally parallel to the second surface of the first microelectronic substrate has a size and shape at least approximately identical to that of the second surface; and

a conductive link between the first and second connection sites.

36. The package of claim 35 wherein the conductive link conforms to at least one of the first surface of the first microelectronic substrate and a material disposed on the first surface of the microelectronic substrate.

37. The package of claim 35 wherein the first and second connection sites face in at least approximately the same direction.

38. The package of claim 35, further comprising:

a first portion of dielectric material disposed on the first microelectronic substrate;

a second portion of dielectric material disposed on the second microelectronic substrate wherein the conductive material conforms to the first and second portions of dielectric material;

a third portion of dielectric material disposed on the conductive material;

a third connection site coupled to the conductive material and the first and second connection sites; and

a volume of flowable conductive material disposed on the third connection site to provide electrical communication with the first and second microelectronic substrates.

39. The package of claim 35 wherein the first microelectronic substrate has an exposed edge between the first and second surfaces, and wherein the package further comprises a microelectronic device external to the assembly and electrically coupled to the assembly while the edge is exposed.

40. The package of claim 35, further comprising a dielectric material disposed between the first surface of the first microelectronic substrate and the second surface of the second microelectronic substrate, the first and second microelectronic substrates being adhered to the dielectric material.

41. The package of claim 35, further comprising an adhesive film disposed between the first and second microelectronic substrates.

42. The package of claim 35 wherein the conductive link includes an elongated conductive structure that extends in three orthogonal directions between the first and second connection sites.

43. The package claim 35 wherein the conductive link is non-self-supporting.

44. An electronic device, comprising:

a housing; and

a microelectronic device package positioned within the housing, the microelectronic device package including;

a first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;

a second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface, the second microelectronic substrate being coupled to the first microelectronic substrate to form a substrate assembly with the second surface of the second microelectronic substrate facing toward the first surface of the first microelectronic substrate; and

a conformal conductive link coupled between the first and second connection sites, the conductive link conforming at least generally to a contour of the substrate assembly.

45. The device of claim 44 wherein the conductive link includes first and second portions of sequentially deposited conductive material.

46. The device of claim 44 wherein the packaged microelectronic device forms at least a part of a processor.

47. The device of claim 44 wherein the packaged microelectronic device forms at least a part of a memory.