Integrated circuit package with solder bumps

• US 6,750,552 B1
• Filed: 12/18/2002
• Issued: 06/15/2004
• Est. Priority Date: 12/18/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Netlogic Microsystems Incorporated (Broadcom, Inc.)
• Inventors: Narayanan, Kollengode Subramanian
• Primary Examiner(s): Vigushin, John B.
• Application Number:
  US10/323,963
• Time in Patent Office: 545 Days
• Field of Search: 257/692, 257/693, 257/697, 257/706, 257/737, 257/738, 257/773, 257/777, 257/778, 257/780, 257/786, 257/707, 228/180.21, 228/180.22
• US Class Current: 257/786
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/28 : Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

A semiconductor package with solder bumps and a method for making the same are described. One embodiment comprises a flip-chip design with a rectangular semiconductor die with a relatively large aspect ratio bonded to a substantially square substrate through solder bumps. In one embodiment, active bumps are concentrated in an area relatively close to the neutral point of the die, for example, in a substantially square area about the neutral point.

Claims

1. An integrated circuit package, comprising:

a semiconductor die having an aspect ratio greater than 1.3; and

a plurality of solder bumps attached to a surface of the die, comprising active bumps arranged regularly on a first region of the surface, wherein the first region comprises a substantially square area about a neutral point of the surface of the die.

2. The integrated circuit package of claim 1, wherein the plurality of solder bumps further comprises non-active bumps arranged regularly about the first region.

3. The integrated circuit package of claim 2, wherein the active bumps carry signals that are not redundant.

4. The integrated circuit package of claim 3, wherein the non-active bumps include bumps that carry redundant signals and bumps that carry no signals.

5. The integrated circuit package of claim 1, further comprising:

a substrate coupled to the die through the plurality of solder bumps, wherein the substrate comprises a ball grid array;

an underfill layer surrounding the plurality of bumps an coupled to the die and the substrate; and

a lid with heat dissipating characteristics coupled to a surface of the die opposite the surface on which the plurality of solder bumps are arranged.

6. The integrated circuit package of claim 2, wherein the active bumps are arranged regularly with a first pitch, and the non-active bumps are arranged regularly with a second pitch.

7. The integrated circuit package of claim 6, wherein the first pitch and the second pitch are the same.

8. The integrated circuit package of claim 6, wherein the first pitch is greater than the second pitch.

9. The integrated circuit package of claim 6, wherein the second pitch is greater than the first pitch.

10. The integrated circuit package of claim 9, wherein the plurality of solder bumps are arranged regularly on the surface with a first pitch along one axis of the die, and a second pitch along another axis of the die.

11. The integrated circuit package of claim 10, wherein the first pitch is approximately 230 microns, and the second pitch is approximately 300 microns.

12. The integrated circuit package of claim 11, wherein the first pitch is along a longer axis of the die, and the second pitch is along a shorter axis of the die.

13. The integrated circuit package of claim 11, wherein the first pitch is along a shorter axis of the die, and the second pitch is along a longer axis of the die.

14. The integrated circuit package of claim 1, wherein the aspect ratio is approximately 2.

15. An integrated circuit package, comprising:

a semiconductor die having an aspect ratio greater than 1.3; and

a plurality of solder bumps attached to a surface of the die, comprising

active bumps arranged regularly on a first region of the surface, wherein the active bumps carry non-redundant signal, and wherein the first region comprises a substantially square area about a neutral point of the surface of the die; and

non-active bumps, wherein the non-active bumps include bumps that carry redundant signals and bumps that carry no signals.

16. The integrated circuit package of claim 15, wherein the non-active bumps are arranged regularly about the first region.

17. The integrated circuit package of claim 15, further comprising:

a substrate coupled to the die through the plurality of solder bumps, wherein the substrate comprises a ball grid array;

an underfill layer surrounding the plurality of bumps an coupled to the die and the substrate; and

a lid with heat dissipating characteristics coupled to a surface of the die opposite the surface on which the plurality of solder bumps are arranged.

18. The integrated circuit package of claim 15, wherein the active bumps are arranged regularly with a first pitch, and the non-active bumps are arranged regularly with a second pitch.

19. The integrated circuit package of claim 18, wherein the first pitch and the second pitch arc the same.

20. The integrated circuit package of claim 18, wherein the first pitch is greater than the second pitch.

21. The integrated circuit package of claim 18, wherein the second pitch is greater than the first pitch.

22. The integrated circuit package of claim 21, wherein the plurality of solder bumps are arranged regularly on the surface with a first pitch along one axis of the die, and a second pitch along another axis of the die.

23. The integrated circuit package of claim 21, wherein the first pitch is approximately 230 microns, and the second pitch is approximately 300 microns.

24. The integrated circuit package of claim 23, wherein the first pitch is along a longer axis of the die, and the second pitch is along a shorter axis of the die.

25. The integrated circuit package of claim 23, wherein the first pitch is along a shorter axis of the die, and the second pitch is along a longer axis of the die.

26. The integrated circuit package of claim 15, wherein the aspect ratio is approximately 2.

27. An integrated circuit package, comprising:

a semiconductor die having an aspect ratio greater than 1.3; and

a plurality of solder bumps attached to a surface of the die, comprising active bumps arranged regularly on a first region of the surface, wherein the active bumps carry non-redundant signal, and wherein the first region comprises a substantially square area about a neutral point of the surface of the die; and

non-active bumps, wherein the non-active bumps include bumps that carry redundant signals and bumps that carry no signals, and wherein the non-active bumps are arranged regularly about the first region.

28. The integrated circuit package of claim 27, further comprising:

a substrate coupled to the die through the plurality of solder bumps, wherein the substrate comprises a ball grid array;

an underfill layer surrounding the plurality of bumps an coupled to the die and the substrate; and

a lid with heat dissipating characteristics coupled to a surface of the die opposite the surface on which the plurality of solder bumps are arranged.

29. The integrated circuit package of claim 27, wherein the active bumps are arranged regularly with a first pitch, and the non-active bumps are arranged regularly with a second pitch.

30. The integrated circuit package of claim 29, wherein the first pitch and the second pitch are the same.

31. The integrated circuit package of claim 29, wherein the first pitch is greater than the second pitch.

32. The integrated circuit package of claim 29, wherein the second pitch is greater than the first pitch.

33. The integrated circuit package of claim 32, wherein the plurality of solder bumps are arranged regularly on the surface with a first pitch along one axis of the die, and a second pitch along another axis of the die.

34. The integrated circuit package of claim 32, wherein the first pitch is approximately 230 microns, and the second pitch is approximately 300 microns.

35. The integrated circuit package of claim 34, wherein the first pitch is along a longer axis of the die, and the second pitch is along a shorter axis of the die.

36. The integrated circuit package of claim 34, wherein the first pitch is along a shorter axis of the die, and the second pitch is along a longer axis of the die.

37. The integrated circuit package of claim 27, wherein the aspect ratio is approximately 2.