Transponder with a changeable circuit configuration

• US 6,750,770 B2
• Filed: 10/01/2002
• Issued: 06/15/2004
• Est. Priority Date: 10/04/2001
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Erdeniz, Pamir, Spiess, Bernhard, Janesch, Werner
• Primary Examiner(s): Hofsass, Jeffery
• Assistant Examiner(s): Previl, Daniel
• Application Number:
  US10/262,386
• Publication Number:
  US 20030067382A1
• Time in Patent Office: 623 Days
• Field of Search: 340/572.3, 340/572.2, 340/572.6, 340/572.1, 340/572.4, 340/572.5, 340/500, 340/540, 340/551, 340/825.68, 340/825.69, 340/5.62, 340/5.63, 340/5.65, 340/5.66, 340/7-2-, 340/7.38, 340/10.1
• US Class Current: 340/572.3
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

A transponder (1) and an integrated circuit (4) have at least one signal channel (5, 6, 7), each signal channel (5, 6, 7) having at least two signal processing stages (25, 26, 27, 28, 29, 30, 31) and at least one signal processing stage (26, 27, 29) configured such as to be activatable and deactivatable, while an associated bypass branch (32, 33, 34), which is also activatable and deactivatable, is provided for each activatable and deactivatable signal processing stage (26, 27, 29), and a microcomputer (36) and a control register (37) controllable by the microcomputer, (36) are provided, by means of which each activatable and deactivatable signal processing stage (26, 27, 29) and the associated bypass branch (32, 33, 34) are activatable and deactivatable in counterphase.

Claims

1. A transponder (1) having at least one signal channel (5, 6, 7), which signal channel (5, 6, 7) having transmission means (8, 9, 10) and at least two signal processing stages (25, 26, 27, 28, 29, 30, 31) connected to the output side of said transmission means (8, 9, 10), wherein at least one signal processing stage (26, 27, 29) is configured such that it is activatable and deactivatable, and wherein for each activatable and deactivatable signal processing stage (26, 27, 29) an associated bypass branch (32, 33, 34) being provided for bypassing the associated signal processing stage (26, 27, 29), which bypass branch (32, 33, 34) is also configured so as to be activatable and deactivatable, and wherein control means (35) are provided by which the at least one activatable and deactivatable signal processing stage (26, 27, 29) and the at least one associated activatable and deactivatable bypass branch (32, 33, 34) are activatable and deactivatable, and wherein the control means (35) and the at least one activatable and deactivatable signal processing stage (26, 27, 29) and the at least one associated activatable and deactivatable bypass branch (32, 33, 34) are so configured such that when one activatable and deactivatable signal processing stage (26, 27, 29) is deactivated the bypass branch (32, 33, 34) associated with this signal processing stage (26, 27, 29) is activated at the same time, and that when one signal processing stage (26, 27, 29) is activated the bypass branch (32, 33, 34) associated with this signal processing stage (26, 27, 29) is deactivated at the same time.

2. A transponder (1) as claimed in claim 1, wherein at least some of the activatable and deactivatable signal processing stages (26, 27, 29) are formed by amplifier stages.

3. A transponder (1) as claimed in claim 1, wherein the control means (35) comprise a microcomputer (36) and a control register (37) controllable by the microcomputer (36), by means of which control register (37) the activatable and deactivatable signal processing stages (26, 27, 29) and the activatable and deactivatable bypass branches (32, 33, 34) are controllable into their activated and deactivated states.

4. A transponder (1) as claimed in claim 3, wherein the control means (35) additionally have timing means (41) connected to the microcomputer (36), and in that the microcomputer (36) is configured so as to register the expiration of a preset time interval, and in that the microcomputer (36), after registering the expiration of said preset time interval, controls the control register (37) such that said control register (37) controls all the signal processing stages (25, 26, 27, 28, 29, 30, 31) so as to switch them to their deactivated state.

5. An integrated circuit (4) for a transponder (1), which integrated circuit (4) having at least one signal channel (5, 6, 7), which signal channel (5, 6, 7) having transmission means (8, 9, 10) and at least two signal processing stages (25, 26, 27, 28, 29, 30, 31) connected to the output side of the transmission means (8, 9, 10), wherein at least one signal processing stage (26, 27, 29) is configured such that it is activatable and deactivatable, and wherein for each activatable and deactivatable signal processing stage (26, 27, 29) an associated bypass branch (32, 33, 34) being provided for bypassing the associated signal processing stage (26, 27, 29), which bypass branch (32, 33, 34) is also configured so as to be activatable and deactivatable, and wherein control means (35) are provided by which the at least one activatable and deactivatable signal processing stage (26, 27, 29) and the at least one associated activatable and deactivatable bypass branch (32, 33, 34) are activatable and deactivatable, and wherein the control means (35) and the at least one activatable and deactivatable signal processing stage (26, 27, 29) and the at least one associated activatable and deactivatable bypass branch (32, 33, 34) are configured such that when one activatable and deactivatable signal processing stage (26, 27, 29) is deactivated the bypass branch (32, 33, 34) associated with this signal processing stage (26, 27, 29) is activated at the same time, and that when one signal processing stage (26, 27, 29) is activated the bypass branch (32, 33, 34) associated with this signal processing stage (26, 27, 29) is deactivated at the same time.

6. An integrated circuit (4) as claimed claim 5, wherein at least some of the activatable and deactivatable signal processing stages (26, 27, 29) are formed by amplifier stages.

7. An integrated circuit (4) as claimed in claim 5, wherein the control means (35) comprise a microcomputer (36) and a control register (37) controllable by the microcomputer (36), by means of which control register (37) the activatable and deactivatable signal processing stages (26, 27, 29) and the activatable and deactivatable bypass branches (32, 33, 34) are controllable into their activated and deactivated states.

8. An integrated circuit (4) as claimed in claim 7, wherein the control means (35) additionally have timing means (41) connected to the microcomputer (36), and in that the microcomputer (36) is configured so as to register the expiration of a preset time interval, and in that the microcomputer (36), after registering the expiration of said preset time interval, controls the control register (37) such that said control register (37) controls all the signal processing stages (25, 26, 27, 28, 29, 30, 31) so as to switch them to their deactivated state.