Serial-to-parallel conversion circuit, and semiconductor display device employing the same

• US 6,750,792 B2
• Filed: 12/17/2002
• Issued: 06/15/2004
• Est. Priority Date: 01/28/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Osame, Mitsuaki, Nagao, Shou, Shionoiri, Yutaka, Azami, Munehiro
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US10/320,491
• Publication Number:
  US 20030122695A1
• Time in Patent Office: 546 Days
• Field of Search: 341/100, 341/101, 327/407, 327/415, 345/502
• US Class Current: 341/100
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Claims

1. A serial-to-parallel conversion circuit for digital data which converts digital data inputted serially at m Hz into 2^y parallel digital data of (m·

2<sup>−

y</sup>) Hz and outputs the 2^y parallel digital data, where letter m denotes a positive number and letter y denotes a natural number;

wherein said serial-to-parallel conversion circuit for digital data operates with a plurality of clock signals and inverted clock signals of said plurality of clock signals of, at the highest (m/2) Hz, and

wherein said serial-to-parallel conversion circuit for digital data is connected to a clock generator which outputs said plurality of clock signals and said inverted clock signals of, at the highest (m/2) Hz, and

wherein said serial-to-parallel conversion circuit is connected to 2y digital data rearrangement switches.

2. A serial-to-parallel conversion circuit for digital data which converts digital data inputted serially at m Hz into 2^y parallel digital data of (m·

2<sup>−

y</sup>) Hz and outputs the 2^y parallel digital data, where letter m denotes a positive number and letter y denotes a natural number;

wherein said serial-to-parallel conversion circuit for digital data operates with a plurality of clock signals and inverted clock signals of said plurality of clock signals of, at the highest, (m/2) Hz and at the lowest, (m·

2<sup>−

y</sup>) Hz, and

wherein said serial-to-parallel conversion circuit for digital data is connected to a clock generator which outputs said plurality of clock signals and said inverted clock signals of, at the highest (m/2) Hz, and

wherein said serial-to-parallel conversion circuit is connected to 2y digital data rearrangement switches.

3. A serial-to-parallel conversion circuit for digital data which converts digital data of respective bits of the x-bit digital data inputted serially at m Hz into 2^y parallel digital data of (m·

2<sup>−

y</sup>) Hz and outputs the 2^y parallel digital data, where letter m denotes a positive number and letters x and y denotes natural numbers;

wherein said serial-to-parallel conversion circuit for digital data comprises x SPC/bit circuits to which the digital data of the respective bits of said x-bit digital data are inputted,

wherein each of said SPC/bit circuits includes first through y-th stage circuits, and

wherein the y-th stage circuit lowers a frequency of 2<sup>y−

1</sup> digital data inputted serially to ½ and

converts the 2<sup>y−

1</sup> digital data into 2^y parallel digital data, and

wherein said serial-to-parallel conversion circuit for digital data is connected to a clock generator which outputs a plurality of clock signals and inverted clock signals of said plurality of clock signals of, at the highest (m/2) Hz, and

wherein said serial-to-parallel conversion circuit is connected to 2y digital data rearrangement switches.

4. A serial-to-parallel conversion circuit for digital data which converts digital data of respective bits of the x-bit digital data inputted serially at m Hz into 2^y parallel digital data of (m·

2<sup>−

y</sup>) Hz and outputs the 2^y parallel digital data, where letter m denotes a positive number and letters x and y denotes natural numbers;

wherein said serial-to-parallel conversion circuit for digital data comprises x SPC/bit circuits to which the digital data of the respective bits of said x-bit digital data are inputted,

wherein each of said SPC/bit circuits includes basic units in a number indicated by Formula (1) given below, and

wherein each of said basic units in the number indicated by Formula (1) lowers a frequency of digital data inputted serially to ½ and

converts the digital data inputted serially into two parallel digital data, and $\begin{array}{cc}\underset{k=1}{\overset{y}{\sum <br><br>}}<br><br>2^{k-1}& \left(1\right)\end{array}$

wherein said serial-to-parallel conversion circuit for digital data is connected to a clock generator which outputs a plurality of clock signals and inverted clock signals of said plurality of clock signals of, at the highest (m/2) Hz, and

wherein said serial-to-parallel conversion circuit is connected to 2y digital data rearrangement switches.

5. A semiconductor display device comprising:

an active matrix circuit in which pixel TFTs are arranged in a matrix shape;

a source signal line driver circuit and a gate signal line driver circuit for driving the active matrix circuit; and

a serial-to-parallel conversion circuit for digital data which converts the digital data inputted serially at m Hz into 2^y parallel digital data of (m·

2<sup>−

y</sup>) Hz and outputs the 2^y parallel digital data, where letter m denotes a positive number and letter y denotes a natural number;

wherein said semiconductor display device operates with a plurality of clock signals and inverted clock signals of said plurality of clock signals of, at the highest, (m/2) Hz,

wherein said serial-to-parallel conversion circuit for digital data is connected to a clock generator which outputs said plurality of clock signals and inverted clock signals of, at the highest (m/2) Hz, and

wherein said serial-to-parallel conversion circuit is connected to the source signal line driver circuit through 2y digital data rearrangement switches.

6. A semiconductor display device comprising:

an active matrix circuit in which pixel TFTs are arranged in a matrix shape,

a source signal line driver circuit and a gate signal line driver circuit for driving the active matrix circuit; and

a serial-to-parallel conversion circuit for digital data which converts the digital data inputted serially at m Hz into 2^y parallel digital data of (m·

2<sup>−

y</sup>) Hz and outputs the 2^y parallel digital data, where letter m denotes a positive number and letter y denotes a natural number;

wherein said semiconductor display device operates with a plurality of clock signals and inverted clock signals of said plurality of clock signals of, at the highest (m/2) Hz and at the lowest, (m·

2<sup>−

y</sup>) Hz, and

wherein said serial-to-parallel conversion circuit for digital data is connected to a clock generator which outputs said plurality of clock signals and inverted clock signals of, at the highest (m/2) Hz,

wherein said serial-to-parallel conversion circuit is connected to the source signal line driver circuit through 2y digital data rearrangement switches.

7. A semiconductor display device comprising:

an active matrix circuit in which pixel TFTs are arranged in a matrix shape,

a source signal line driver circuit and a gate signal line driver circuit for driving the active matrix circuit, and

a serial-to-parallel conversion circuit for digital data which converts digital data of respective bits of the x-bit digital data inputted serially at m Hz into 2^y parallel digital data of (m·

2<sup>−

y</sup>) Hz and outputs the 2^y parallel digital data, where letter m denotes a positive number and letters x and y denote natural numbers;

wherein said serial-to-parallel conversion circuit for digital data includes x SPC/bit circuits to which the digital data of the respective bits of said x-bit digital data are inputted,

wherein each of said SPC/bit circuits includes first through y-th stage circuits, and

wherein the y-th stage circuit lowers a frequency of 2<sup>y−

1</sup> digital data inputted serially to ½ and

converts the 2<sup>y−

1</sup> digital data inputted serially into the 2^y parallel digital data, and

wherein said serial-to-parallel conversion circuit for digital data is connected to a clock generator which outputs a plurality of clock signals and inverted clock signals of said plurality of clock signals of, at the highest (m/2) Hz, and

wherein said serial-to-parallel conversion circuit is connected to the source signal line driver circuit through 2y digital data rearrangement switches.

8. A semiconductor display device comprising:

an active matrix circuit in which pixel TFTs are arranged in a matrix shape;

a source signal line driver circuit and a gate signal line driver circuit for driving the active matrix circuit, and

a serial-to-parallel conversion circuit for digital data which converts digital data of respective bits of the x-bit digital data inputted serially at m Hz into 2^y parallel digital data of (m·

2<sup>−

y</sup>) Hz outputs the 2^y parallel digital data, where letter m denotes a positive number and letters x and y denote natural numbers;

said serial-to-parallel conversion circuit for digital data including x SPC/bit circuits to which the digital data of the respective bits of said x-bit digital data are inputted,

each of said SPC/bit circuits including basic units in a number indicated by Formula (1) given below, and

each of said basic units in the number indicated by Formula (1) lowering a frequency of digital data inputted serially to ½ and

converts the digital data inputted serially into two parallel digital data, and $\begin{array}{cc}\underset{k=1}{\overset{y}{\sum <br><br>}}<br><br>2^{k-1}& \left(1\right)\end{array}$

wherein said serial-to-parallel conversion circuit for digital data is connected to a clock generator which outputs a plurality of clock signals and inverted clock signals of said plurality of clock signals of, at the highest (m/2) Hz, and

wherein said serial-to-parallel conversion circuit is connected to the source signal line driver circuit 2y digital data rearrangement switches.