Active-passive imager pixel array with small groups of pixels having short common bus lines

• US 6,750,912 B1
• Filed: 09/30/1999
• Issued: 06/15/2004
• Est. Priority Date: 09/30/1999
• Status: Expired due to Term

• Current Assignee: RE Secured Networks LLC
• Original Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Inventors: Tomasini, Alfredo, Tennant, William E., Kozlowski, Lester
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): MISLEH, JUSTIN P
• Application Number:
  US09/408,919
• Time in Patent Office: 1,720 Days
• Field of Search: 348/294, 348/302, 348/308, 348/303, 348/304, 348/309, 348/241, 348/243, 348/245, 257/281, 257/292, 257/215, 257/230, 257/229, 257/231, 257/232, 257/233, 257/291, 257/294, 250/208.1
• US Class Current: 348/300
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

A shared output visible imager pixel array combines a high optical fill factor with low read noise. A relatively small group of pixels are connected to a relatively short common bus line. An amplifier located in close proximity with the pixels is connected to the common bus line and shared among the pixels. By reducing the amount of amplifier circuitry associated with each pixel, the optical fill factor is increased. Also, since the bus line is relatively short, the bus capacitance is much lower relative to the traditional passive-pixel designs. On average, the transistor count per pixel can be less than two, for large arrays.

Claims

1. An imager array comprising:

a plurality of pixel groups, each pixel group comprising;

a plurality of pixels located in close proximity to each other and connected to a common bus line, the common bus line having a relatively low bus capacitance; and

an amplifier connected to the common bus line, wherein the amplifier is located in close proximity to the plurality of pixels;

wherein the plurality of pixels comprises four pixels, such that one pixel is a dark pixel used to subtract off an amplifier offset associated with the amplifier.

2. The imager array of claim 1, wherein the amplifier is a FET configured in a source-follower configuration.

3. The imager array of claim 2, wherein a pixel comprises a photodiode and an access transistor.

4. The imager array of claim 1, wherein the common bus line is physically much shorter than a bus line in a standard passive pixel imager.

5. The imager array of claim 4, wherein the plurality of pixels comprises three pixels.

6. The imager array of claim 4, wherein the average number of transistors per pixel in the array is less than two.

7. The imager array of claim 3, wherein the access transistor comprises a p transistor in a shallow n-well, in order to reduce blooming.

8. The imager array of claim 1, wherein the amplifier is located within the dark pixel area.

9. The imager of claim 4, herein each pixel group further comprises an access transistor, and each of the plurality of pixels is connected to the common bus line through a separate access transistor.

10. The imager array of claim 1, wherein a pixel comprises a photocapacitor.

11. An imager array comprising:

a plurality of pixel groups, each pixel group comprising;

a common bus line, the common bus line being shorter than a bus line in a standard passive pixel imager and having a relatively low bus capacitance;

a plurality of passive pixels located in close proximity to each other and connected to the common bus line;

an amplifier FET connected to the common bus line, wherein the amplifier FET is located in close proximity to the plurality of passive pixels;

a reset FET connected to the common bus line; and

an output access FET connected to the amplifier FET and an output bus;

wherein the plurality of passive pixels comprises four pixels, such that one pixel is a dark pixel used to subtract off an amplifier offset associated with the amplifier FET.

12. The imager array of claim 11, wherein the amplifier FET is configured in a source-follower configuration.

13. The imager array of claim 12, wherein a passive pixel comprises a photodiode and an access transistor.

14. The imager array of claim 13, wherein the photodiode is a source diode of the access transistor.

15. The imager array of claim 13, wherein the plurality of passive pixels 2 comprises three pixels.

16. The imager array of claim 13, wherein the average number of transistors per pixel in the array is less than two.

17. The imager array of claim 16, wherein the access transistor comprises a p transistor in a shallow n-well, in order to reduce blooming.

18. The imager array of claim 11, wherein the amplifier, reset and access circuitry for each pixel group is located within the dark pixel area.

19. The imager array of claim 11, wherein a passive pixel comprises a photocapacitor.

20. An imager array having a relatively high optical fill factor and low bus capacitance, the imager array comprising:

a plurality of pixel groups, each pixel group comprising;

a plurality of passive pixels located in close proximity to each other and connected to a common bus line, the common bus line being relatively short; and

an amplifier connected to the common bus line, wherein the amplifier is located in close proximity to the plurality of passive pixels;

wherein the average number of transistors per pixel in the array is less than two,

wherein the plurality of passive pixels comprise four pixels, such that one pixel is a dark pixel used to subtract off an amplifier offset associated with the amplifier.