Arrangement of integrated circuits in a memory module

• US 6,751,113 B2
• Filed: 03/07/2002
• Issued: 06/15/2004
• Est. Priority Date: 03/07/2002
• Status: Expired due to Term

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Bhakta, Jayesh R., Pauley, Robert S. Jr.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/094,512
• Publication Number:
  US 20030169614A1
• Time in Patent Office: 831 Days
• Field of Search: 365/51, 365/63, 365/78, 711/2, 711/5, 711/104, 711/111, 711/115
• US Class Current: 365/63
• CPC Class Codes: H05K 1/0266 Marks, test patterns or identification means
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09409 Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
• CPC Class Codes: H05K 2201/09709 Staggered pads, lands or terminals; Parallel conductors in different planes
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

Claims

1. A memory module comprising:

a generally planar printed circuit board having a line of bilateral symmetry which bisects the printed circuit board into a first lateral half and a second lateral half;

a first row of memory integrated circuits identical to one another, the first row positioned on a first side of the printed circuit board, the first row perpendicular to the line of bilateral symmetry and bilaterally symmetric with respect to the line of bilateral symmetry, the integrated circuits of the first row having a first orientation direction;

a second row of memory integrated circuits identical to the integrated circuits of the first row, the second row positioned on the first side of the printed circuit board, the second row perpendicular to the line of bilateral symmetry and bilaterally symmetric with respect to the line of bilateral symmetry, the integrated circuits of the second row having a second orientation direction rotated in a plane parallel to the printed circuit board by approximately 180 decrees from the first orientation direction;

a first addressing register coupled to the integrated circuits of the first row on the first lateral half and to the integrated circuits of the second row on the first lateral half; and

a second addressing register coupled to the integrated circuits of the first row of the second lateral half and to the integrated circuits of the second row of the second lateral half,

wherein the first addressing register addresses a first range of data bits and a second range of data bits non-contiguous with the first range of data bits, and wherein the second addressing register addresses a third range of data bits and a fourth range of data bits non-contiguous with the third range of data bits, the first range, the second range, the third range, and the fourth range having the same number of data bits.

3. The memory module of claim 1, wherein the integrated circuits are Double Data Rate SDRAM.

2. A memory module comprising:

a generally planar printed circuit board having a line of bilateral symmetry which bisects the printed circuit board into a first lateral half and a second lateral half;

a first row of memory integrated circuits identical to one another, the first row positioned on a first side of the printed circuit board, the first row perpendicular to the line of bilateral symmetry and bilaterally symmetric with respect to the line of bilateral symmetry, the integrated circuits of the first row having a first orientation direction;

a second row of memory integrated circuits identical to the integrated circuits of the first row, the second row positioned on the first side of the printed circuit board, the second row perpendicular to the line of bilateral symmetry and bilaterally symmetric with respect to the line of bilateral symmetry, the integrated circuits of the second row having a second orientation direction rotated in a plane parallel to the printed circuit board by approximately 180 degrees from the first orientation direction;

a first addressing register coupled to the integrated circuits of the first row on the first lateral half and to the integrated circuits of the second row on the first lateral half;

a second addressing register coupled to the integrated circuits of the first row of the second lateral half and to the integrated circuits of the second row of the second lateral half,

a third row of integrated circuits identical to the integrated circuits of the first row, the third row positioned on a second side of the printed circuit board, the third row perpendicular to the line of bilateral symmetry and bilaterally symmetric with respect to the line of bilateral symmetry, the integrated circuits of the third row having a third orientation direction; and

a fourth row of integrated circuits identical to the integrated circuits of the first row, the fourth row positioned on the second side of the printed circuit board, the fourth row perpendicular to the line of bilateral symmetry and bilaterally symmetric with respect to the line of bilateral symmetry, the integrated circuits of the fourth row having a fourth orientation direction rotated in a plane parallel to the printed circuit board by approximately 180 degrees from the third orientation direction,

wherein the first addressing register is coupled to the integrated circuits of the third row on the first lateral half and to the integrated circuits of the fourth row on the first lateral half and the second addressing register is coupled to the integrated circuits of the third row on the second lateral half and to the integrated circuits of the fourth row on the second lateral half.

4. The memory module of claim 7, wherein the integrated circuits are Double Data Rate SDRAM.