Nonvolatile semiconductor memory device

• US 6,751,122 B2
• Filed: 02/21/2003
• Issued: 06/15/2004
• Est. Priority Date: 10/30/2002
• Status: Expired due to Term

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawai, Koichi, Hosono, Koji, Imamiya, Kenichi
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US10/371,306
• Publication Number:
  US 20040085814A1
• Time in Patent Office: 480 Days
• Field of Search: 365/185.09, 365/185.05, 365/185.17, 365/185.2, 365/185.33, 365/189.01, 365/189.05, 365/189.07, 365/200
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification

Abstract

The nonvolatile semiconductor memory device includes a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in which initial setup data specified to determine operation conditions of the device is to be written. The device further includes a detection circuit which detects turn-on of power. The device further includes a readout circuit which reads out the initial setup data from the initial setup data region of the memory cell array upon detecting power-on by the detection circuit. The device further includes a determination circuit which determines whether the initial setup data read out by the readout circuit is effective or ineffective. The device further includes a setup circuit which sets up the device in an operative-prohibiting status when the initial setup data is determined as ineffective by the determination circuit.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in which initial setup data specified to determine operation conditions of the device is to be written;

a detection circuit which detects turn-on of power;

a readout circuit which reads out the initial setup data from the initial setup data region of the memory cell array upon detecting power-on by the detection circuit;

a determination circuit which determines whether the initial setup data read out by the readout circuit is effective or ineffective; and

a setup circuit which sets up the device in an operative-prohibiting status when the initial setup data is determined as ineffective by the determination circuit.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array is an electrically programmable NAND type flash memory.

3. The nonvolatile semiconductor memory device according to claim 1, wherein the setup circuit is a status output circuit having a chip status fixed at a fail status.

4. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a data latch circuit which maintains the initial setup data read out by the readout circuit; and

a control circuit which controls the initial setup operation, the control circuit transferring the initial setup data to the data latch circuit when the initial setup data read out by the readout circuit is determined effective.

5. The nonvolatile semiconductor memory device according to claim 4, wherein the setup circuit has a function setting the chip status at “

pass”

when the initial setup data is determined effective by the determination circuit; and

the control circuit executes the initial setup operation upon the setting of the pass status by the setup circuit.

6. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array comprises a redundancy cell array configured to replace a defective cell;

and the initial setup data includes control data which replaces the defective cell with the redundancy cell array.

7. The nonvolatile semiconductor memory device according to claim 6, wherein the initial setup data includes the control data and reference data which confirms the effectiveness of the control data;

and the determination circuit determines whether the initial setup data is effective or ineffective based on whether or not the control data and the reference data correspond to each other.

8. The nonvolatile semiconductor memory device according to claim 7, wherein the reference data is complementary to the control data.

9. The nonvolatile semiconductor memory device according to claim 1, wherein the initial setup data includes control data controlling data write, erase and read operations.

10. The nonvolatile semiconductor memory device according to claim 9, wherein the initial setup data includes the control data and reference data confirming the effectiveness of the control data;

and the determination circuit determines whether the initial setup data is effective or ineffective based on whether or not the control data and the reference data correspond to each other.

11. The nonvolatile semiconductor memory device according to claim 10, wherein the reference data is complementary to the control data.

12. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array contains a plurality of planes each comprising the initial setup data region.

13. The nonvolatile semiconductor memory device according to claim 12, wherein the same initial setup data is written in the initial setup data region arranged in each of the plurality of planes;

and the determination circuit determines that the initial setup data is effective or ineffective based on the initial setup data written in the initial setup data region.

14. The nonvolatile semiconductor memory device according to claim 1, further comprising a register which stores a control signal from the outside, wherein the register comprises a storage-prohibition circuit configured to prohibit all or part of the control signal from being stored by setting the device at an operation-prohibiting status.

15. The nonvolatile semiconductor memory device according to claim 14, wherein the control signal is a command input data.

16. The nonvolatile semiconductor memory device according to claim 1, further comprising an output buffer which stores an output signal;

and the output buffer comprises an output fixing circuit which fixes output from the output buffer by setting the device at an operation-prohibiting status by the setup circuit.

17. The nonvolatile semiconductor memory device according to claim 1, further comprising an interior timer circuit and an interior timer circuit setup circuit which sets the interior timer circuit at a nonactive status by setting the device at an operation-prohibiting status by the setup circuit.

18. The nonvolatile semiconductor memory device according to claim 1, further comprising a voltage generation circuit and a voltage generation circuit setup circuit which sets up the voltage generation circuit at a nonactive state by setting the device at an operation-prohibiting status by the setup circuit.

19. The nonvolatile semiconductor memory device according to claim 4, wherein the control circuit outputs a busy signal to the outside until the initial setup operation finishes.