Method and system for low power refresh of dynamic random access memories

• US 6,751,143 B2
• Filed: 04/11/2002
• Issued: 06/15/2004
• Est. Priority Date: 04/11/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Blodgett, Greg A., Morgan, Donald M.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US10/122,943
• Publication Number:
  US 20030193829A1
• Time in Patent Office: 796 Days
• Field of Search: 365/230.04, 365/222, 365/227, 365/230.06
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Claims

1. A dynamic random access memory (“

DRAM”

) comprising;

an array of memory cells arranged in rows and columns, each row of memory cells having a respective word line that is activated to couple the memory cells in the row to one of a respective pair of complimentary digit lines;

a row decoder coupled to receive a row address and being operable to activate a word line corresponding thereto;

a column decoder coupled to receive a column address and being operable to select a memory cell in a column corresponding thereto;

an input/output control circuit including a sense amplifier for each column of memory cells in the array, the input/output control circuit coupling data between the memory cells in the array and a data bus;

a row address counter coupled to the row decoder, the row address counter being operable to increment by one in a full density mode and to increment by two in a half density mode, the row address counter being operable to generate row addresses corresponding to the count of the row address counter;

a refresh control circuit operable in either a full density mode or a half density mode, the refresh control circuit being operable to cause data to be transferred from memory cells in each row of the array in which data are stored to another row of memory cells when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit further being operable to refresh each row of memory cells selected by a row address from the row address counter in the full density mode and to simultaneously refresh two rows of memory cells selected by a row address from the row address counter in the half density mode; and

a refresh timer operable to control the rate at which the rows of memory cells are refreshed in the full density mode and in the half density mode.

2. The DRAM of claim 1 wherein the row decoder comprises:

an even row address decoder coupled to the word lines for the even-numbered rows of the memory array; and

an odd row address decoder coupled to the word lines for the odd-numbered rows of the memory array.

3. The DRAM of claim 1 wherein the row decoder is operable in the full density mode to reorder each row address applied to the DRAM device by making the most significant bit of the row address the least significant bit of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address, the row addresses generated by the row decoder corresponding to the reordered row addresses.

4. The DRAM of claim 1 wherein, when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit is operable to cause data from each row of memory cells in the array in which data are stored to be transferred to an adjacent row of memory cells.

5. The DRAM of claim 1 wherein the row address counter comprises:

a first counter operable to increment by one responsive to an auto refresh command; and

a second counter operable to increment by one in the full density mode and to increment by two in the half density mode.

6. The DRAM of claim 1 wherein the refresh timer is operable to cause the refresh of rows of memory cells at a first rate in the full density mode and at a second rate in the half density mode, the second rate being slower than the first rate.

7. The DRAM of claim 1 further comprising a mode register that may be externally programmed, the mode register being coupled to the refresh control circuit to permit operation in the half density mode responsive to predetermined mode data being stored in the mode register.

8. The DRAM of claim 1 wherein the DRAM comprises a synchronous DRAM.

9. A dynamic random access memory (“

DRAM”

) comprising;

an array of memory cells arranged in rows and columns, each row of memory cells having a respective word line that is activated to couple the memory cells in the row to one of a respective pair of complimentary digit lines;

a row decoder coupled to receive a row address and being operable to activate a word line corresponding thereto, the row decoder being operable to reorder each row address applied to the DRAM device by making the most significant bit of the row address the least significant bit of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address, the row decoder activating word lines for respective rows of memory cells according to the reordered row address;

a column decoder coupled to receive a column address and being operable to select a memory cell in a column corresponding thereto;

an input/output control circuit including a sense amplifier for each column of memory cells in the array, the input/output control circuit coupling data between the memory cells in the array and a data bus;

a row address counter coupled to the row decoder, the row address counter being operable to generate row addresses corresponding to the count of the row address counter;

a refresh control circuit operable in either a full density mode or a half density mode, the refresh control circuit being operable to cause data to be transferred from memory cells in each row of the array in which data are stored to an adjacent row of memory cells when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit further being operable to refresh each row of memory cells selected by a row address from the row address counter in the full density mode and to simultaneously refresh two adjacent rows of memory cells selected by a row address from the row address counter in the half density mode; and

a refresh timer operable to cause the rows of memory cells to be refreshed at a first rate in the full density mode and at a second rate in the half density mode, the second rate being slower than the first rate.

10. The DRAM of claim 9 wherein the row decoder comprises:

an even row address decoder coupled to the word lines for the even-numbered rows of the memory array; and

an odd row address decoder coupled to the word lines for the odd-numbered rows of the memory array.

11. The DRAM of claim 9 wherein the row address counter comprises:

a first counter operable to increment by one responsive to an auto refresh command; and

a second counter operable to increment by one in the full density mode and to increment by two in the half density mode.

12. The DRAM of claim 9 further comprising a mode register that may be externally programmed, the mode register being coupled to the refresh control circuit to permit operation in the half density mode responsive to predetermined mode data being stored in the mode register.

13. The DRAM of claim 9 wherein the DRAM comprises a synchronous DRAM.

14. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a dynamic random access memory (“

DRAM”

) device coupled to the processor through the processor bus, the DRAM device comprising;

an array of memory cells arranged in rows and columns, each row of memory cells having a respective word line that is activated to couple the memory cells in the row to one of a respective pair of complimentary digit lines;

a row decoder coupled to receive a row address and being operable to activate a word line corresponding thereto;

a column decoder coupled to receive a column address and being operable to select a memory cell in a column corresponding thereto;

an input/output control circuit including a sense amplifier for each column of memory cells in the array, the input/output control circuit coupling data between the memory cells in the array and a data bus;

a row address counter coupled to the row decoder, the row address counter being operable to increment by one in a full density mode and to increment by two in a half density mode, the row address counter being operable to generate row addresses corresponding to the count of the row address counter;

a refresh control circuit operable in either a full density mode or a half density mode, the refresh control circuit being operable to cause data to be transferred from memory cells in each row of the array in which data are stored to another row of memory cells when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit further being operable to refresh each row of memory cells selected by a row address from the row address counter in the full density mode and to simultaneously refresh two rows of memory cells selected by a row address from the row address counter in the half density mode; and

a refresh timer operable to control the rate at which the rows of memory cells are refreshed in the full density mode and in the half density mode.

15. The computer system of claim 14 wherein the row decoder comprises:

an even row address decoder coupled to the word lines for the even-numbered rows of the memory array; and

an odd row address decoder coupled to the word lines for the odd-numbered rows of the memory array.

16. The computer system of claim 14 wherein the row decoder is operable in the full density mode to reorder each row address applied to the DRAM device by making the most significant bit of the row address the least significant bit of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address, the row addresses generated by the row decoder corresponding to the reordered row addresses.

17. The computer system of claim 14 wherein, when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit is operable to cause data from each row of memory cells in the array in which data are stored to be transferred to an adjacent row of memory cells.

18. The computer system of claim 14 wherein the row address counter comprises:

a first counter operable to increment by one responsive to an auto refresh command; and

a second counter operable to increment by one in the full density mode and to increment by two in the half density mode.

19. The computer system of claim 14 wherein the refresh timer is operable to cause the refresh of rows of memory cells at a first rate in the full density mode and at a second rate in the half density mode, the second rate being slower than the first rate.

20. The computer system of claim 14 further comprising a mode register that may be externally programmed, the mode register being coupled to the refresh control circuit to permit operation in the half density mode responsive to predetermined mode data being stored in the mode register.

21. The computer system of claim 14 wherein the DRAM comprises a synchronous DRAM.

22. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a dynamic random access memory (“

DRAM”

) device coupled to the processor through the processor bus, the DRAM device comprising;

an array of memory cells arranged in rows and columns, each row of memory cells having a respective word line that is activated to couple the memory cells in the row to one of a respective pair of complimentary digit lines;

a row decoder coupled to receive a row address and being operable to activate a word line corresponding thereto, the row decoder being operable to reorder each row address applied to the DRAM device by making the most significant bit of the row address the least significant bit of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address, the row decoder activating word lines for respective rows of memory cells according to the reordered row address;

a column decoder coupled to receive a column address and being operable to select a memory cell in a column corresponding thereto;

an input/output control circuit including a sense amplifier for each column of memory cells in the array, the input/output control circuit coupling data between memory cells in the array and a data bus;

a row address counter coupled to the row decoder, the row address counter being operable to generate row addresses corresponding to the count of the row address counter;

a refresh control circuit operable in either a full density mode or a half density mode, the refresh control circuit being operable to cause data to be transferred from memory cells in each row of the array in which data are stored to an adjacent row of memory cells when switching from operation in the full density mode to operation in the half density mode, the refresh control circuit further being operable to refresh each row of memory cells selected by a row address from the row address counter in the full density mode and to simultaneously refresh two adjacent rows of memory cells selected by a row address from the row address counter in the half density mode; and

a refresh timer operable to cause the rows of memory cells to be refreshed at a first rate in the full density mode and at a second rate in the half density mode, the second rate being slower than the first rate.

23. The DRAM of claim 22 wherein the row decoder comprises:

an even row address decoder coupled to the word lines for the even-numbered rows of the memory array; and

an odd row address decoder coupled to the word lines for the odd-numbered rows of the memory array.

24. The computer system of claim 22 wherein the row address counter comprises:

a first counter operable to increment by one responsive to an auto refresh command; and

a second counter operable to increment by one in the full density mode and to increment by two in the half density mode.

25. The computer system of claim 22 further comprising a mode register that may be externally programmed, the mode register being coupled to the refresh control circuit to permit operation in the half density mode responsive to predetermined mode data being stored in the mode register.

26. The computer system of claim 22 wherein the DRAM comprises a synchronous DRAM.