Circuits and method to protect a gate dielectric antifuse

• US 6,751,150 B2
• Filed: 08/29/2002
• Issued: 06/15/2004
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W., Porter, John D.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/231,756
• Publication Number:
  US 20040042317A1
• Time in Patent Office: 656 Days
• Field of Search: 365/225.7, 365/145, 257/530
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse. The antifuse includes a layer of gate dielectric between the first terminal and the second terminal. The embodiments of the present invention protect a gate dielectric antifuse.

Claims

1. A method of operating an antifuse circuit comprising:

coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

controlling current in the antifuse with a program driver circuit coupled to the second terminal of the antifuse; and

shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse.

2. The method of claim 1 wherein:

coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse through a common bus line during a programming mode of operation, the antifuse comprising a layer of oxide between the gate electrode and a well in a substrate; and

shunting current around the antifuse further comprises shunting current around the antifuse with a plurality of p-channel transistors coupled as diodes in series between the gate electrode and the well.

3. The method of claim 2, further comprising:

coupling a supply voltage to the common bus line during an active mode of operation and reading the antifuse with a read circuit coupled to the program driver circuit;

coupling an intermediate voltage between the elevated voltage and the supply voltage to a gate terminal of a high-voltage transistor in the program driver circuit from a gate bias circuit to protect the high-voltage transistor during the programming mode, the high-voltage transistor being coupled to the well; and

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor in the program driver circuit during the programming mode to program the antifuse.

4. The method of claim 1, further comprising:

coupling a supply voltage to a common bus line coupled to the first terminal of the antifuse during an active mode of operation and reading the antifuse with a read circuit coupled to the program driver circuit;

coupling an intermediate voltage between the elevated voltage and the supply voltage to a gate terminal of a high-voltage transistor in the program driver circuit from a gate bias circuit to protect the high-voltage transistor during a programming mode of operation, the high-voltage transistor being coupled to the second terminal of the antifuse;

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor in the program driver circuit during the programming mode to program the antifuse;

generating an analog voltage in the bypass circuit comprising a first impedance coupled between the first terminal of the antifuse and a second impedance, the second impedance being coupled between the first impedance and a supply voltage; and

wherein coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse through the common bus line during the programming mode, the antifuse comprising a layer of oxide between the gate electrode and a well in a substrate; and

wherein shunting current around the antifuse further comprises coupling current from a node between the first impedance and the second impedance in the bypass circuit to the program driver circuit between the high-voltage transistor and the n-channel transistor.

5. A method of operating an antifuse circuit comprising:

coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

controlling current in the antifuse with a program driver circuit coupled to the second terminal of the antifuse; and

shunting current around the antifuse with a plurality of diodes coupled in series between the first terminal of the antifuse and the program driver circuit to protect the antifuse.

6. The method of claim 5 wherein:

coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse through a common bus line during a programming mode of operation, the antifuse comprising a layer of oxide between the gate electrode and a well in a substrate; and

shunting current around the antifuse further comprises shunting current around the antifuse with a plurality of p-channel transistors coupled as diodes in series between the gate electrode and the well.

7. The method of claim 6, further comprising:

coupling a supply voltage to the common bus line during an active mode of operation and reading the antifuse with a read circuit coupled to the program driver circuit;

coupling an intermediate voltage between the elevated voltage and the supply voltage to a gate terminal of a high-voltage transistor in the program driver circuit from a gate bias circuit to protect the high-voltage transistor during the programming mode, the high-voltage transistor being coupled to the well; and

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor in the program driver circuit during the programming mode to program the antifuse.

8. A method of operating an antifuse circuit comprising:

coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

controlling current in the antifuse with a program driver circuit coupled to the second terminal of the antifuse;

generating an analog voltage in a pre-charge circuit coupled to the first terminal of the antifuse; and

coupling current from the pre-charge circuit to the program driver circuit to shunt current around the antifuse to protect the antifuse.

9. The method of claim 8, further comprising:

coupling a supply voltage to a common bus line coupled to the first terminal of the antifuse during an active mode of operation and reading the antifuse with a read circuit coupled to the program driver circuit; and

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor in the program driver circuit during the programming mode to program the antifuse.

10. The method of claim 9, further comprising coupling an intermediate voltage between the elevated voltage and the supply voltage to a gate terminal of a high-voltage transistor in the program driver circuit from a gate bias circuit to protect the high-voltage transistor during a programming mode of operation, the high-voltage transistor being coupled to the second terminal of the antifuse.

11. The method of claim 9 wherein:

generating an analog voltage further comprises generating the analog voltage in the pre-charge circuit comprising a first impedance coupled between the first terminal of the antifuse and a second impedance, the second impedance being coupled between the first impedance and the supply voltage;

coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse through the common bus line during the programming mode, the antifuse comprising a layer of oxide between the gate electrode and a well in a substrate; and

coupling current from the pre-charge circuit further comprises coupling current from a node between the first impedance and the second impedance in the pre-charge circuit to the program driver circuit between the high-voltage transistor and the n-channel transistor.

12. An antifuse circuit comprising:

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit;

a program driver circuit coupled to the second terminal of the antifuse to control current in the antifuse; and

a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to shunt current around the antifuse during a programming mode to protect the antifuse.

13. The antifuse circuit of claim 12 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a supply voltage during an active mode of operation;

the bypass circuit comprises a plurality of p-channel transistors coupled as diodes in series between the gate electrode and the well;

the program driver circuit comprises;

a high-voltage transistor coupled to the well; and

an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor to program the antifuse during the programming mode.

14. The antifuse circuit of claim 13, further comprising:

a read circuit coupled to the high-voltage transistor to read the antifuse during the active mode; and

a gate bias circuit coupled between the common bus line and a gate terminal of the high-voltage transistor to couple an intermediate voltage between the elevated voltage and the supply voltage to the gate terminal of the high-voltage transistor during the programming mode to protect the high-voltage transistor.

15. The antifuse circuit of claim 12 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a supply voltage during an active mode of operation;

the program driver circuit comprises;

a high-voltage transistor coupled to the well; and

an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor to program the antifuse during the programming mode; and

the bypass circuit comprises;

a first impedance coupled between the gate electrode and a second impedance, the second impedance being coupled between the first impedance and a supply voltage; and

a node between the first impedance and the second impedance in the bypass circuit coupled to the program driver circuit between the high-voltage transistor and the n-channel transistor.

16. An antifuse circuit comprising:

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit;

a program driver circuit coupled to the second terminal of the antifuse to control current in the antifuse; and

a plurality of diodes coupled in series between the first terminal of the antifuse and the program driver circuit to shunt current around the antifuse to protect the antifuse.

17. The antifuse circuit of claim 16 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a supply voltage during an active mode of operation; and

the plurality of diodes comprises a plurality of p-channel transistors coupled as diodes in series between the gate electrode and the well.

18. The antifuse circuit of claim 17 wherein the program driver circuit comprises:

a high-voltage transistor coupled to the well; and

an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor to program the antifuse during the programming mode.

19. The antifuse circuit of claim 18, further comprising:

a read circuit coupled to the high-voltage transistor to read the antifuse during the active mode; and

a gate bias circuit coupled between the common bus line and a gate terminal of the high-voltage transistor to couple an intermediate voltage between the elevated voltage and the supply voltage to the gate terminal during the programming mode to protect the high-voltage transistor.

20. An antifuse circuit comprising:

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit;

a pre-charge circuit coupled to the first terminal of the antifuse, the pre-charge circuit comprising a first impedance coupled between the first terminal of the antifuse and a second impedance, the second impedance being coupled between the first impedance and a reference voltage; and

a program driver circuit coupled to the second terminal of the antifuse to control current in the antifuse, the program driver circuit being coupled to receive current from a node between the first impedance and the second impedance of the pre-charge circuit to shunt the current around the antifuse to protect the antifuse.

21. The antifuse circuit of claim 20 wherein the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a supply voltage during an active mode of operation.

22. The antifuse circuit of claim 21 wherein the program driver circuit comprises:

a first high-voltage transistor coupled to the well; and

an n-channel transistor coupled to the first high-voltage transistor to control current flowing through the antifuse and the first high-voltage transistor to program the antifuse during the programming mode.

23. The antifuse circuit of claim 22 wherein the pre-charge circuit comprises:

a first adjustable resistor coupled to the common bus line;

a first diode-connected high-voltage transistor coupled to the first adjustable resistor;

a second adjustable resistor coupled between the first diode-connected high-voltage transistor and the supply voltage; and

a pair of diode-connected high-voltage transistors coupled in series between a node and the first high-voltage transistor in the program driver circuit, the node being coupled between the first adjustable resistor and the first diode-connected high-voltage transistor, the pair of diode-connected high-voltage transistors to couple current to the program driver circuit.

24. The antifuse circuit of claim 23, further comprising a transistor coupled between the first diode-connected high-voltage transistor and a voltage reference to couple the voltage reference to the first diode-connected high-voltage transistor during the active mode to draw current from the pre-charge circuit to the voltage reference.

25. The antifuse circuit of claim 22, further comprising:

a read circuit coupled to the first high-voltage transistor to read the antifuse during the active mode; and

a gate bias circuit coupled between the common bus line and a gate terminal of the first high-voltage transistor to couple an intermediate voltage between the elevated voltage and the supply voltage to the gate terminal of the first high-voltage transistor during the programming mode to protect the first high-voltage transistor.

26. A memory device comprising:

an array of memory cells in a memory device;

an address decoder coupled to the array in the memory device to decode address signals to access the memory cells;

a plurality of input/output paths coupled to the array to couple data to the memory cells;

an input/output control circuit coupled to the array in the memory device to control the data based on control signals;

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit in the memory device;

a program driver circuit coupled to the second terminal of the antifuse to control current in the antifuse; and

a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to shunt current around the antifuse during a programming mode to protect the antifuse.

27. The memory device of claim 26 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a supply voltage during an active mode of operation;

the bypass circuit comprises a plurality of p-channel transistors coupled as diodes in series between the gate electrode and the well;

the program driver circuit comprises;

a high-voltage transistor coupled to the well; and

an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor to program the antifuse during the programming mode.

28. The memory device of claim 27, further comprising:

a read circuit coupled to the high-voltage transistor to read the antifuse during the active mode; and

a gate bias circuit coupled between the common bus line and a gate terminal of the high-voltage transistor to couple an intermediate voltage between the elevated voltage and the supply voltage to the gate terminal of the high-voltage transistor during the programming mode to protect the high-voltage transistor.

29. The memory device of claim 26 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a supply voltage during an active mode of operation;

the program driver circuit comprises;

a high-voltage transistor coupled to the well; and

an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor to program the antifuse during the programming mode; and

the bypass circuit comprises;

a first impedance coupled between the gate electrode and a second impedance, the second impedance being coupled between the first impedance and a supply voltage; and

a node between the first impedance and the second impedance in the bypass circuit coupled to the program driver circuit between the high-voltage transistor and the n-channel transistor.

30. The memory device of claim 26 wherein the memory device comprises a static random access memory device.

31. The memory device of claim 26 wherein:

the input/output control circuit is coupled to receive a write enable signal, an output enable signal, and a chip enable signal to control the data; and

further comprising a power down circuit in the memory device coupled to the array to control the memory device during a power-down mode.

32. A method of operating a memory device comprising:

accessing memory cells in an array of memory cells in a memory device by decoding address signals in an address decoder coupled to the array in the memory device;

coupling data to the memory cells through a plurality of input/output paths coupled to the array;

controlling the data on the input/output paths with an input/output control circuit;

coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit in the memory device, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

controlling current in the antifuse with a program driver circuit coupled to the second terminal of the antifuse; and

shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse.

33. The method of claim 32 wherein:

coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse through a common bus line during a programming mode of operation, the antifuse comprising a layer of oxide between the gate electrode and a well in a substrate; and

shunting current around the antifuse further comprises shunting current around the antifuse with a plurality of p-channel transistors coupled as diodes in series between the gate electrode and the well.

34. The method of claim 33, further comprising:

coupling a supply voltage to the common bus line during an active mode of operation and reading the antifuse with a read circuit coupled to the program driver circuit;

coupling an intermediate voltage between the elevated voltage and the supply voltage to a gate terminal of a high-voltage transistor in the program driver circuit from a gate bias circuit to protect the high-voltage transistor during the programming mode, the high-voltage transistor being coupled to the well; and

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor in the program driver circuit during the programming mode to program the antifuse.

35. The method of claim 32, further comprising:

coupling a supply voltage to a common bus line coupled to the first terminal of the antifuse during an active mode of operation and reading the antifuse with a read circuit coupled to the program driver circuit;

coupling an intermediate voltage between the elevated voltage and the supply voltage to a gate terminal of a high-voltage transistor in the program driver circuit from a gate bias circuit to protect the high-voltage transistor during a programming mode of operation, the high-voltage transistor being coupled to the second terminal of the antifuse;

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor in the program driver circuit during the programming mode to program the antifuse;

generating an analog voltage in the bypass circuit comprising a first impedance coupled between the first terminal of the antifuse and a second impedance, the second impedance being coupled between the first impedance and a supply voltage; and

wherein coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse through the common bus line during the programming mode, the antifuse comprising a layer of oxide between the gate electrode and a well in a substrate; and

wherein shunting current around the antifuse further comprises coupling current from a node between the first impedance and the second impedance in the bypass circuit to the program driver circuit between the high-voltage transistor and the n-channel transistor.

36. The method of claim 32 wherein accessing memory cells further comprises accessing memory cells in an array of memory cells in a static random access memory device.

37. The method of claim 32 wherein:

controlling the data further comprises controlling the data on the input/output paths in response to a write enable signal, an output enable signal, and a chip enable signal coupled to the input/output control circuit; and

further comprising controlling the memory device with a power down circuit in the memory device coupled to the array during a power-down mode.

38. A system comprising:

a processor;

a memory system coupled to the processor;

an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit in the memory system;

a program driver circuit coupled to the second terminal of the antifuse to control current in the antifuse; and

a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to shunt current around the antifuse during a programming mode to protect the antifuse.

39. The system of claim 38 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a supply voltage during an active mode of operation;

the bypass circuit comprises a plurality of p-channel transistors coupled as diodes in series between the gate electrode and the well;

the program driver circuit comprises;

a high-voltage transistor coupled to the well; and

an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor to program the antifuse during the programming mode.

40. The system of claim 39, further comprising:

a read circuit coupled to the high-voltage transistor to read the antifuse during the active mode; and

a gate bias circuit coupled between the common bus line and a gate terminal of the high-voltage transistor to couple an intermediate voltage between the elevated voltage and the supply voltage to the gate terminal of the high-voltage transistor during the programming mode to protect the high-voltage transistor.

41. The system of claim 38 wherein:

the antifuse further comprises a layer of oxide between a gate electrode that is coupled to a common bus line in the antifuse circuit and a well in a substrate, the common bus line being coupled to receive the elevated voltage during a programming mode of operation and a supply voltage during an active mode of operation;

the program driver circuit comprises;

a high-voltage transistor coupled to the well; and

an n-channel transistor coupled to the high-voltage transistor to control current flowing through the antifuse and the high-voltage transistor to program the antifuse during the programming mode; and

the bypass circuit comprises;

a first impedance coupled between the gate electrode and a second impedance, the second impedance being coupled between the first impedance and a supply voltage; and

a node between the first impedance and the second impedance in the bypass circuit coupled to the program driver circuit between the high-voltage transistor and the n-channel transistor.

42. The system of claim 38, further comprising:

a display unit;

an input/output subsystem; and

a bus coupled to the processor, the memory system, the display unit, and the input/output subsystem.

43. The system of claim 38 wherein the processor comprises a microprocessor.

44. A method of operating a system comprising:

exchanging signals between a processor and a memory system coupled together;

coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit in the memory system, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;

controlling current in the antifuse with a program driver circuit coupled to the second terminal of the antifuse; and

shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse.

45. The method of claim 44 wherein:

coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse through a common bus line during a programming mode of operation, the antifuse comprising a layer of oxide between the gate electrode and a well in a substrate; and

shunting current around the antifuse further comprises shunting current around the antifuse with a plurality of p-channel transistors coupled as diodes in series between the gate electrode and the well.

46. The method of claim 45, further comprising:

coupling a supply voltage to the common bus line during an active mode of operation and reading the antifuse with a read circuit coupled to the program driver circuit;

coupling an intermediate voltage between the elevated voltage and the supply voltage to a gate terminal of a high-voltage transistor in the program driver circuit from a gate bias circuit to protect the high-voltage transistor during the programming mode, the high-voltage transistor being coupled to the well; and

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor in the program driver circuit during the programming mode to program the antifuse.

47. The method of claim 44, further comprising:

coupling a supply voltage to a common bus line coupled to the first terminal of the antifuse during an active mode of operation and reading the antifuse with a read circuit coupled to the program driver circuit;

coupling an intermediate voltage between the elevated voltage and the supply voltage to a gate terminal of a high-voltage transistor in the program driver circuit from a gate bias circuit to protect the high-voltage transistor during a programming mode of operation, the high-voltage transistor being coupled to the second terminal of the antifuse;

controlling current flowing through the antifuse and the high-voltage transistor with an n-channel transistor coupled to the high-voltage transistor in the program driver circuit during the programming mode to program the antifuse;

generating an analog voltage in the bypass circuit comprising a first impedance coupled between the first terminal of the antifuse and a second impedance, the second impedance being coupled between the first impedance and a supply voltage; and

wherein coupling an elevated voltage further comprises coupling the elevated voltage to a gate electrode of the antifuse through the common bus line during the programming mode, the antifuse comprising a layer of oxide between the gate electrode and a well in a substrate; and

wherein shunting current around the antifuse further comprises coupling current from a node between the first impedance and the second impedance in the bypass circuit to the program driver circuit between the high-voltage transistor and the n-channel transistor.

48. The method of claim 44 wherein exchanging signals further comprises exchanging signals between the processor, the memory system, an input/output subsystem, and a display unit over a bus coupled between the processor, the memory system, the input/output subsystem, and the display unit.

49. The method of claim 44 wherein exchanging signals comprises exchanging signals between a microprocessor and a memory system coupled together.

50. An antifuse circuit comprising:

an antifuse comprising a layer of gate dielectric between a first terminal coupled to a common bus line to receive an elevated voltage and a second terminal in an antifuse circuit;

a program driver circuit coupled to the second terminal of the antifuse to program the antifuse;

a read circuit coupled to the program driver circuit to read the antifuse; and

means for shunting current from the common bus line to the program driver circuit around the antifuse to protect the antifuse.