Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode

• US 6,751,159 B2
• Filed: 10/26/2001
• Issued: 06/15/2004
• Est. Priority Date: 10/26/2001
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Schaefer, Scott E., Farrell, Todd D.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US10/039,815
• Publication Number:
  US 20030081492A1
• Time in Patent Office: 963 Days
• Field of Search: 365/238.5, 365/230.02, 365/230.03, 365/230.05, 365/185.12
• US Class Current: 365/238.5
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2254 Calibration

Abstract

A memory device includes 4 memory banks each of which includes first and second arrays of memory cells. A mode register is programmed with a bit that selects a high-power, large-page operating mode or a low-power, small-page operating mode. In the high-power mode, a row decoder is coupled to the row lines in both the first and second arrays. In the low-power mode, the row decoder is coupled to the row lines in only one of the arrays as determined by the state of an array select signal. The array select signal corresponds to the most significant bit of the column address, but it is applied to the memory device at the time the row address is applied to the memory device. Sense amplifiers coupled to the first and second arrays may also be selectively enabled when the row lines for the corresponding array are coupled to the row decoder.

Claims

1. A system for selecting between first and second arrays of memory cells each of which includes a set of row lines, the system comprising:

a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode;

a row decoder coupled to receive a row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;

a column decoder coupled to receive a column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and

a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being coupled to receive the mode select signal and an array select signal, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

2. The system of claim 1 wherein the array select signal comprises a most significant bit of the column address.

3. The system of claim 1 wherein the mode select circuit comprises a mode register the may be programmed by an externally applied signal to store a bit corresponding to the mode select signal.

4. The system of claim 3 wherein the externally applied signal comprises a bank address bit.

5. The system of claim 1 wherein the array select signal is received by the switching circuit contemporaneously with the row decoder receiving the row address.

6. The system of claim 1 wherein the switching circuit is further operable to couple the rows lines of the second array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and being operable to couple the rows lines of the first array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

7. The system of claim 6 wherein the reference voltage comprises ground potential.

8. The system of claim 1 wherein the switching circuit comprises:

a control circuit receiving the mode select signal and the array select signal, the control circuit being operable to generate first and second control signals each having a first state responsive to the mode select signal indicating operation in the first mode, the control circuit being operable to generate the first control signal having the first state and the second control signal having a second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the control circuit being operable to generate the first control signal having the second state and the second control signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state;

a first multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a first reference voltage, a set of output terminals coupled to respective row lines of the first array, and a control terminal coupled to receive the first control signal, the first multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the first control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the first control signal having the second state; and

a second multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a second reference voltage, a set of output terminals coupled to respective row lines of the second array, and a control terminal coupled to receive the second control signal, the second multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the second control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the second control signal having the second state.

9. The system of claim 8 wherein the first and second reference voltages comprise ground potential.

10. The system of claim 1, further comprising:

a first set of sense amplifiers coupled to respective digit lines in the first array, the sense amplifiers in the first set having an enable terminal receiving a first enable signal having first and second states, power being coupled to the sense amplifiers in the first set responsive to the first enable signal having the first state, and power being decoupled from the sense amplifiers in the first set responsive to the first enable signal having the second state;

a second set of sense amplifiers coupled to respective digit lines in the second array, the sense amplifiers in the second set having an enable terminal receiving a second enable signal having first and second states, power being coupled to the sense amplifiers in the second set responsive to the second enable signal having the first state, and power being decoupled from the sense amplifiers in the second set responsive to the second enable signal having the second state; and

a control circuit receiving the mode select signal and the array select signal, the control circuit being operable to generate first and second enable signals each having the first state responsive to the mode select signal indicating operation in the first mode, the control circuit being operable to generate the first enable signal having the first state and the second enable signal having the second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the control circuit being operable to generate the first enable signal having the second state and the second enable signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

11. A system for selecting between first and second arrays of memory cells each of which includes a set of row lines, the system comprising:

a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode;

a row decoder coupled to receive a row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;

a column decoder coupled to receive a column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and

an array control circuit coupled to the row lines of the first and second arrays, the array control circuit being coupled to receive the mode select signal and an array select signal, the array control circuit being operable to allow the row activate signal to be applied to a row line in the first and second arrays responsive to the mode select signal indicating operation in the first mode, the array control circuit being operable to allow the row activate signal to be applied to a row line in the first array but not to a row line in the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the array control circuit being operable to allow the row activate signal to be applied to a row line in the second array but not to a row line in the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

12. The array selecting system of claim 11 wherein the array select signal comprises a most significant bit of the column address.

13. The array selecting system of claim 11 wherein the mode select circuit comprises a mode register the may be programmed by an externally applied signal to store a bit corresponding to the mode select signal.

14. The array selecting system of claim 13 wherein the externally applied signal comprises a bank address bit.

15. The array selecting system of claim 11 wherein the array select signal is received by the array control circuit contemporaneously with the row decoder receiving the row address.

16. The array selecting system of claim 11 wherein the array control circuit is further operable to couple the rows lines of the second array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and being operable to couple the rows lines of the first array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

17. The array selecting system of claim 16 wherein the reference voltage comprises ground potential.

18. The array selecting system of claim 11 wherein the array control circuit comprises:

a multiplexer control circuit receiving the mode select signal and the array select signal, the multiplexer control circuit being operable to generate first and second control signals each having a first state responsive to the mode select signal indicating operation in the first mode, the multiplexer control circuit being operable to generate the first control signal having the first state and the second control signal having a second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the multiplexer control circuit being operable to generate the first control signal having the second state and the second control signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state;

a first multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a first reference voltage, a set of output terminals coupled to respective row lines of the first array, and a control terminal coupled to receive the first control signal, the first multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the first control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the first control signal having the second state; and

a second multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a second reference voltage, a set of output terminals coupled to respective row lines of the second array, and a control terminal coupled to receive the second control signal, the second multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the second control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the second control signal having the second state.

19. The array selecting system of claim 18 wherein the first and second reference voltages comprise ground potential.

20. The array selecting system of claim 11, further comprising:

a first set of sense amplifiers coupled to respective digit lines in the first array, the sense amplifiers in the first set having an enable terminal receiving a first enable signal having first and second states, power being coupled to the sense amplifiers in the first set responsive to the first enable signal having the first state, and power being decoupled from the sense amplifiers in the first set responsive to the first enable signal having the second state;

a second set of sense amplifiers coupled to respective digit lines in the second array, the sense amplifiers in the second set having an enable terminal receiving a second enable signal having first and second states, power being coupled to the sense amplifiers in the second set responsive to the second enable signal having the first state, and power being decoupled from the sense amplifiers in the second set responsive to the second enable signal having the second state; and

a column control circuit receiving the mode select signal and the array select signal, the column control circuit being operable to generate first and second enable signals each having the first state responsive to the mode select signal indicating operation in the first mode, the column control circuit being operable to generate the first enable signal having the first state and the second enable signal having the second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the column control circuit being operable to generate the first enable signal having the second state and the second enable signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

21. A memory addressing system for addressing a memory bank having first and second arrays, each of which includes a set of row lines, the memory addressing system comprising:

a memory controller generating a row address having a plurality of row address bits followed by a column address having a plurality of column address bits, the memory controller generating an array select signal prior to generating the plurality of column address bits, the array select signal corresponding to a column address bit and having either a first state or a second state;

a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode;

a row decoder coupled to the memory controller to receive the row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;

a column decoder coupled to the memory controller to receive the column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and

a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

22. The memory addressing system of claim 21 wherein the memory controller is operable to generate a bit corresponding to a most significant column address bit as the array select signal.

23. The memory addressing system of claim 21 wherein the mode select circuit comprises a mode register the may be programmed by an externally applied signal to store a bit corresponding to the mode select signal.

24. The memory addressing system of claim 23 wherein the externally applied signal comprises a bank address bit.

25. The memory addressing system of claim 21 wherein the memory controller is operable to generate the array select signal at the time the memory controller it operable to generate the row address bits.

26. The memory addressing system of claim 21 wherein the switching circuit is further operable to couple the rows lines of the second array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and being operable to couple the rows lines of the first array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

27. The memory addressing system of claim 26 wherein the reference voltage comprises ground potential.

28. The memory addressing system of claim 21 wherein the switching circuit comprises:

a control circuit receiving the mode select signal and the array select signal, the control circuit being operable to generate first and second control signals each having a first state responsive to the mode select signal indicating operation in the first mode, the control circuit being operable to generate the first control signal having the first state and the second control signal having a second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the control circuit being operable to generate the first control signal having the second state and the second control signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state;

a first multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a first reference voltage, a set of output terminals coupled to respective row lines of the first array, and a control terminal coupled to receive the first control signal, the first multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the first control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the first control signal having the second state; and

a second multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a second reference voltage, a set of output terminals coupled to respective row lines of the second array, and a control terminal coupled to receive the second control signal, the second multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the second control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the second control signal having the second state.

29. The memory addressing system of claim 28 wherein the first and second reference voltages comprise ground potential.

30. The memory addressing system of claim 21, further comprising:

a first set of sense amplifiers coupled to respective digit lines in the first array, the sense amplifiers in the first set having an enable terminal receiving a first enable signal having first and second states, power being coupled to the sense amplifiers in the first set responsive to the first enable signal having the first state, and power being decoupled from the sense amplifiers in the first set responsive to the first enable signal having the second state;

a second set of sense amplifiers coupled to respective digit lines in the second array, the sense amplifiers in the second set having an enable terminal receiving a second enable signal having first and second states, power being coupled to the sense amplifiers in the second set responsive to the second enable signal having the first state, and power being decoupled from the sense amplifiers in the second set responsive to the second enable signal having the second state; and

a control circuit receiving the mode select signal and the array select signal, the control circuit being operable to generate first and second enable signals each having the first state responsive to the mode select signal indicating operation in the first mode, the control circuit being operable to generate the first enable signal having the first state and the second enable signal having the second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the control circuit being operable to generate the first enable signal having the second state and the second enable signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

31. A memory device, comprising:

a row address circuit operable to receive row address signals applied to an external terminal and to decode the row address signals to generate a row activate signal at one of a plurality of output terminals corresponding to the row address;

a column address circuit operable to receive column address signals applied to an external terminal and to decode the column address signals to generate a column activate signal at one of a plurality of output terminals corresponding to the column address;

first and second arrays of memory cells operable to store data written to or read from the array at a location determined by the row address and the column address, each of the first and second arrays having a respective set of row lines;

a data path circuit operable to couple data signals corresponding to the data between the first and second arrays and an external data terminal;

a command signal generator operable to generate a sequence of control signals corresponding to command signals applied to an external terminal; and

a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode; and

an array control circuit coupled to the row lines of the first and second arrays, the array control circuit being coupled to receive the mode select signal and an array select signal, the array control circuit being operable to allow the row activate signal to be applied to a row line in the first and second arrays responsive to the mode select signal indicating operation in the first mode, the array control circuit being operable to allow the row activate signal to be applied to a row line in the first array but not to a row line in the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the array control circuit being operable to allow the row activate signal to be applied to a row line in the second array but not to a row line in the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

32. The memory device of claim 31 wherein the array select signal comprises a most significant bit of the column address.

33. The memory device of claim 31 wherein the mode select circuit comprises a mode register the may be programmed by an externally applied signal to store a bit corresponding to the mode select signal.

34. The memory device of claim 33 wherein the externally applied signal comprises a bank address bit.

35. The memory device of claim 31 wherein the array select signal is received by the array control circuit contemporaneously with the row decoder receiving the row address.

36. The memory device of claim 31 wherein the array control circuit is further operable to couple the rows lines of the second array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and being operable to couple the rows lines of the first array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

37. The memory device of claim 36 wherein the reference voltage comprises ground potential.

38. The memory device of claim 31 wherein the array control circuit comprises:

a multiplexer control circuit receiving the mode select signal and the array select signal, the multiplexer control circuit being operable to generate first and second control signals each having a first state responsive to the mode select signal indicating operation in the first mode, the multiplexer control circuit being operable to generate the first control signal having the first state and the second control signal having a second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the multiplexer control circuit being operable to generate the first control signal having the second state and the second control signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state;

a first multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a first reference voltage, a set of output terminals coupled to respective row lines of the first array, and a control terminal coupled to receive the first control signal, the first multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the first control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the first control signal having the second state; and

a second multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a second reference voltage, a set of output terminals coupled to respective row lines of the second array, and a control terminal coupled to receive the second control signal, the second multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the second control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the second control signal having the second state.

39. The memory device of claim 38 wherein the first and second reference voltages comprise ground potential.

40. The memory device of claim 31, further comprising:

a first set of sense amplifiers coupled to respective digit lines in the first array, the sense amplifiers in the first set having an enable terminal receiving a first enable signal having first and second states, power being coupled to the sense amplifiers in the first set responsive to the first enable signal having the first state, and power being decoupled from the sense amplifiers in the first set responsive to the first enable signal having the second state;

a second set of sense amplifiers coupled to respective digit lines in the second array, the sense amplifiers in the second set having an enable terminal receiving a second enable signal having first and second states, power being coupled to the sense amplifiers in the second set responsive to the second enable signal having the first state, and power being decoupled from the sense amplifiers in the second set responsive to the second enable signal having the second state; and

a column control circuit receiving the mode select signal and the array select signal, the column control circuit being operable to generate first and second enable signals each having the first state responsive to the mode select signal indicating operation in the first mode, the column control circuit being operable to generate the first enable signal having the first state and the second enable signal having the second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the column control circuit being operable to generate the first enable signal having the second state and the second enable signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

41. The memory device of claim 31 wherein the memory device comprises a dynamic random access memory.

42. The memory device of claim 41 wherein the dynamic random access memory comprises a synchronous dynamic random access memory.

43. The memory device of claim 31, further comprising a plurality of memory banks each of which includes first and second arrays and a respective array control circuit coupled to the first and second arrays of each memory bank.

44. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;

a memory controller generating a row address having a plurality of row address bits followed by a column address having a plurality of column address bits, the memory controller generating an array select signal prior to generating the plurality of column address bits, the array select signal corresponding to a column address bit and having either a first state or a second state; and

a memory device coupled to the memory controller, the memory device comprising;

a row decoder coupled to the memory controller to receive the row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;

a column decoder coupled to the memory controller to receive the column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and

first and second arrays of memory cells operable to store data written to or read from the array at a location determined by the row address and the column address, each of the first and second arrays having a respective set of row lines;

a data path circuit operable to couple data signals corresponding to the data between the first and second arrays and an external data terminal;

a command signal generator operable to generate a sequence of control signals corresponding to command signals applied to an external terminal;

a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode; and

a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

45. The computer system of claim 44 wherein the memory controller is operable to generate a bit corresponding to a most significant column address bit as the array select signal.

46. The computer system of claim 44 wherein the mode select circuit comprises a mode register the may be programmed by an externally applied signal to store a bit corresponding to the mode select signal.

47. The computer system of claim 46 wherein the externally applied signal comprises a bank address bit.

48. The computer system of claim 44 wherein the memory controller is operable to generate the array select signal at the time the memory controller it operable to generate the row address bits.

49. The computer system of claim 44 wherein the switching circuit is further operable to couple the rows lines of the second array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and being operable to couple the rows lines of the first array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

50. The computer system of claim 49 wherein the reference voltage comprises ground potential.

51. The computer system of claim 44 wherein the switching circuit comprises:

a control circuit receiving the mode select signal and the array select signal, the control circuit being operable to generate first and second control signals each having a first state responsive to the mode select signal indicating operation in the first mode, the control circuit being operable to generate the first control signal having the first state and the second control signal having a second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the control circuit being operable to generate the first control signal having the second state and the second control signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state;

a first multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a first reference voltage, a set of output terminals coupled to respective row lines of the first array, and a control terminal coupled to receive the first control signal, the first multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the first control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the first control signal having the second state; and

a second multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a second reference voltage, a set of output terminals coupled to respective row lines of the second array, and a control terminal coupled to receive the second control signal, the second multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the second control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the second control signal having the second state.

52. The computer system of claim 51 wherein the first and second reference voltages comprise ground potential.

53. The computer system of claim 44, further comprising:

a first set of sense amplifiers coupled to respective digit lines in the first array, the sense amplifiers in the first set having an enable terminal receiving a first enable signal having first and second states, power being coupled to the sense amplifiers in the first set responsive to the first enable signal having the first state, and power being decoupled from the sense amplifiers in the first set responsive to the first enable signal having the second state;

a second set of sense amplifiers coupled to respective digit lines in the second array, the sense amplifiers in the second set having an enable terminal receiving a second enable signal having first and second states, power being coupled to the sense amplifiers in the second set responsive to the second enable signal having the first state, and power being decoupled from the sense amplifiers in the second set responsive to the second enable signal having the second state; and

a control circuit receiving the mode select signal and the array select signal, the control circuit being operable to generate first and second enable signals each having the first state responsive to the mode select signal indicating operation in the first mode, the control circuit being operable to generate the first enable signal having the first state and the second enable signal having the second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the control circuit being operable to generate the first enable signal having the second state and the second enable signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

54. The computer system of claim 44 wherein the memory device comprises a dynamic random access memory.

55. The computer system of claim 44, wherein the memory device comprises a plurality of memory banks each of which includes first and second arrays and a respective switching circuit coupled to the first and second arrays of each memory bank.

56. In a memory device, a method of selecting between first and second arrays of memory cells, the method comprising:

determining within the memory device whether the memory device is to operate in either a first mode or a second mode;

receiving a row address, a column address, and an array select signal, the row address and the array select signal being received prior to the column address being received;

opening a row of memory cells in the first and second arrays responsive to determining within the memory device that the memory device is to operate in the first mode;

opening a row of memory cells in the first array but not the second array responsive to receiving an array select signal having a first state after determining within the memory device that the memory device is to operate in the second mode; and

opening a row of memory cells in the second array but not the first array responsive to receiving an array select signal having a second state after determining within the memory device that the memory device is to operate in the second mode.

57. The method of claim 56 wherein the array select signal comprises a most significant bit of the column address.

58. The method of claim 56 wherein the act of determining within the memory device whether the memory device is to operate in either a first mode or a second mode comprises:

programming a mode register to either a first state or a second state prior to normal operation of the memory device;

examining the mode register during normal operation of the memory device to determine the programmed state of the mode register;

determining that the memory device is to operate in the first mode if the mode register has been determined to be programmed in the first state; and

determining that the memory device is to operate in the second mode if the mode register has been determined to be programmed in the second state.

59. The method of claim 58 wherein the act of programming the mode register to either the first state or the second state comprises:

externally applying a bank address bit to the mode register; and

storing the externally applied bank address bit in the mode register.

60. The method of claim 56 wherein the act of receiving the array select signal comprises receiving the array select signal contemporaneously with the row address.

61. The method of claim 56, further comprising:

applying power to sense amplifiers coupled to the first array responsive to either determining within the memory device that the memory device is to operate in the first mode or receiving the array select signal having the first state after determining within the memory device that the memory device is to operate in the second mode; and

applying power to sense amplifiers coupled to the first array responsive to either determining within the memory device that the memory device is to operate in the first mode or receiving the array select signal having the second state after determining within the memory device that the memory device is to operate in the second mode;

removing power from the sense amplifiers coupled to the first array responsive to receiving the array select signal having the second state after determining within the memory device that the memory device is to operate in the second mode; and

removing power from the sense amplifiers coupled to the second array responsive to receiving the array select signal having the first state after determining within the memory device that the memory device is to operate in the second mode.

62. A method of operating a memory device having first and second memory cell arrays having respective sets of row lines, the method comprising:

determining within the memory device whether the memory device is to operate in either a first mode or a second mode;

receiving a row address, a column address, and an array select signal, the row address and the array select signal being received prior to the column address being received;

coupling a row activate signal to respective row lines in the first and second arrays responsive to determining within the memory device that the memory device is to operate in the first mode;

coupling a row activate signal to a row line in the first array but not to a row line in the second array responsive to receiving an array select signal having a first state after determining within the memory device that the memory device is to operate in the second mode; and

coupling a row activate signal to a row line in the second array but not to a row line in the first array responsive to receiving an array select signal having a second state after determining within the memory device that the memory device is to operate in the second mode.

63. The method of claim 62 wherein the array select signal comprises a most significant bit of the column address.

64. The method of claim 62 wherein the act of determining within the memory device whether the memory device is to operate in either a first mode or a second mode comprises:

programming a mode register to either a first state or a second state prior to normal operation of the memory device;

examining the mode register during normal operation of the memory device to determine the programmed state of the mode register;

determining that the memory device is to operate in the first mode if the mode register has been determined to be programmed in the first state; and

determining that the memory device is to operate in the second mode if the mode register has been determined to be programmed in the second state.

65. The method of claim 64 wherein the act of programming the mode register to either the first state or the second state comprises:

externally applying a bank address bit to the mode register; and

storing the externally applied bank address bit in the mode register.

66. The method of claim 62 wherein the act of receiving the array select signal comprises receiving the array select signal contemporaneously with the row address.

67. The method of claim 66 wherein the act of not coupling the activate signals to a row line in the first array comprises coupling the row lines in the first array to a reference voltage, and wherein the act of not coupling the activate signals to a row line in the second array comprises coupling the row lines in the second array to a reference voltage.

68. The method of claim 62 wherein the act of not coupling the activate signals to a row line in the first array comprises isolating the row lines in the first array from row activate signals, and wherein the act of not coupling the activate signals to a row line in the second array comprises isolating the row lines in the second array from row activate signals.

69. The method of claim 62, further comprising:

applying power to sense amplifiers coupled to the first array responsive to either determining within the memory device that the memory device is to operate in the first mode or receiving the array select signal having the first state after determining within the memory device that the memory device is to operate in the second mode; and

applying power to sense amplifiers coupled to the first array responsive to either determining within the memory device that the memory device is to operate in the first mode or receiving the array select signal having the second state after determining within the memory device that the memory device is to operate in the second mode;

removing power from the sense amplifiers coupled to the first array responsive to receiving the array select signal having the second state after determining within the memory device that the memory device is to operate in the second mode; and

removing power from the sense amplifiers coupled to the second array responsive to receiving the array select signal having the first state after determining within the memory device that the memory device is to operate in the second mode.