Phase re-alignment of SONET/SDH network switch without pointer manipulation

• US 6,751,238 B1
• Filed: 04/20/2000
• Issued: 06/15/2004
• Est. Priority Date: 04/20/2000
• Status: Expired due to Fees

• Current Assignee: Aztech Partners, Inc.
• Original Assignee: Aztech Partners, Inc.
• Inventors: Hughes, Phillip P., Lipp, Robert J.
• Primary Examiner(s): Vu, Huy D.
• Assistant Examiner(s): Philpott, Justin
• Application Number:
  US09/553,501
• Time in Patent Office: 1,517 Days
• Field of Search: 370/355, 370/374, 370/394, 370/395.51, 370/395.62, 370/395.71, 370/508, 370/510, 370/512, 370/516, 370/518, 370/519, 370/537, 370/540, 370/541
• US Class Current: 370/541
• CPC Class Codes: H04J 2203/0005 Switching elements
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06
• CPC Class Codes: H04J 3/0691 Synchronisation in a TDM node

Abstract

A large network switch has switch elements distributed across several chassis separated by perhaps several hundred meters. A generated sync pulse arrives at different switch elements at different times, creating skew. The latency of data through the network switch is set to match the frame period of SONET frames. SONET frames are adjusted at the ingress ports to align the data pointer to the beginning of the frame. The frame is divided along row boundaries into separate cell-packets that are routed across the switch fabric to the egress port. The packets are held in a buffer at the egress port until the next frame begins with the next sync pulse. Upon receiving the next sync pulse, the frame is transmitted. No pointer adjustment is needed by the egress port. A row number is used as a sequence number for the cell-packet to allow the egress port to re-order the cell-packets when transmitting the frame. Since no pointer manipulation is needed at the egress port, pointer management is simplified.

Claims

1. A skew-tolerant distributed network switch comprising:

a plurality of network interface ports containing;

ingress ports, coupled to receive input data streams from external sources;

egress ports, coupled to transmit data streams over external links;

switch elements, coupled together and to the ingress and egress ports, to form a switch fabric for switching cell-packets from an ingress port to an egress port;

each network interface port receiving a clock pulse that is synchronized to the data streams, wherein different network interface ports receive the clock pulse with varying skews to the data streams;

input buffers, in the ingress ports, for buffering data from the input data streams;

a packetizer, coupled to the input buffers, for forming cell-packets from the input data stream, the cell-packets being injected into the switch fabric by the ingress ports and routed to the egress ports through the switch elements;

wherein the input data streams are organized into data frames that comprise one or more of the cell-packets;

wherein the clock pulse is for indicating a frame boundary in the input data streams;

output buffers, in the egress ports, for receiving and storing data from the cell-packets routed through the switch fabric, the cell-packets being re-ordered into a same sequence order as within the input data streams;

transmitters, in the egress ports and coupled to the external links, for transmitting data from the cell-packets stored in the output buffers over the external links; and

clock triggers, receiving the clock pulse, and coupled to the transmitters, for delaying transmission of the data in the frames until a clock pulse is received by the clock trigger;

wherein the cell-packets from a frame are formed and injected into the switch fabric after a first clock pulse is received by the ingress port, but before the next clock pulse is received by the ingress port;

wherein the cell-packets are received by the egress port before the next clock pulse;

wherein the next clock pulse is a next pulse after the first clock pulse,

whereby the cell-packets are formed and routed through the switch fabric within one clock period and whereby clock skews are tolerated by delaying transmission of the data from the egress ports until a next clock pulse is received.

2. The skew-tolerant distributed network switch of claim 1 further comprising:

a header generator, coupled to the packetizer, for attaching a header to each cell-packet, the header including;

an internal address of an egress port that the cell-packet is being routed to through the switch fabric;

a sequence number, indicating a sequence order of the cell-packet in the frame from the input data stream;

wherein the egress port removes the header from the cell-packet and uses the sequence number to re-order the cell-packet into the same sequence order as the input data stream,

whereby internal headers are generated and attached to the cell-packets to indicate the sequence order of the cell-packets.

3. The skew-tolerant distributed network switch of claim 2 further comprising:

an offset clock pulse, having a same frequency as the clock pulse but also having a phase offset from the clock pulse;

wherein some of the network interface ports receive the offset clock pulse;

wherein cell-packets from a frame are formed and injected into the switch fabric after a first clock pulse is received by the ingress port, but before the offset clock pulse is received by the ingress port;

wherein the cell-packets are received by the egress port before the offset clock pulse;

whereby the cell-packets are formed and routed through the switch fabric within one clock period adjusted for a skew between the clock pulse and the offset clock pulse.

4. The skew-tolerant distributed network switch of claim 3 wherein the header of the cell-packets further comprise:

a frame-sequence number, indicating a sequence order of the frame in a sequence of frames;

whereby the frame-sequence number allows for ordering frames when phase offset exceeds one clock period.

5. The skew-tolerant distributed network switch of claim 2 wherein the packetizer forms a first cell-packet after a first clock pulse is received;

wherein the clock trigger causes the transmitter to start transmitting a first cell-packet of a previous frame, the transmitter then transmitting other cell-packets in order,

whereby the first cell-packet at an ingress port is injected no sooner than a start of transmission at the egress port of the first cell-packet of the previous frame.

6. The skew-tolerant distributed network switch of claim 2 wherein the ingress port further comprises:

a routing table, for generating the internal address of the egress port for the cell-packets in response to an external destination for the data stream,

whereby the cell-packets are routed through the switch fabric.

7. The skew-tolerant distributed network switch of claim 6 wherein the input data stream is a Synchronous Optical NETwork (SONET) data stream and the frame is a SONET frame,

wherein the clock pulse is a SONET sync pulse,

whereby SONET sync-pulse skew is tolerated by delaying transmission at the egress port until a next SONET sync pulse.

8. A The skew-tolerant distributed network switch of claim 7 wherein the input data stream is a SONET data stream in an OC-n format having n interleaved STS-1 frames between each pair of clock pulses, wherein n is a positive integer;

wherein the header of the cell-packet also includes;

a STS-n number, indicating an interleave number of a STS-1 frame in an OC-n input data stream for the cell-packet;

wherein the egress ports re-order the cell-packets using the sequence number that indicates a packetization order and the STS-n number that indicates the interleave order of the cell-packets,

whereby interleaved SONET frames are packetized, routed through the switch fabric, and re-ordered.

9. The skew-tolerant distributed network switch of claim 8 wherein the packetization order is an order of data rows in a frame.

10. The skew-tolerant distributed network switch of claim 9 wherein the input data stream contains a plurality of data rows between each pair of clock pulses, wherein each data row contains an overhead data portion and a payload data portion;

wherein the packetizer attaches the header to a cell payload formed from the overhead and payload data portions of one data row in the input data stream,

whereby one cell-packet is formed for each data row.

11. The skew-tolerant distributed network switch of claim 10 wherein the sequence number in the header of the cell-packets is a data row number indicating a data row of the input data stream that contains the overhead and payload data portions of the payload within the cell-packet,

whereby data row numbers indicate the sequence order.

12. The skew-tolerant distributed network switch of claim 10 wherein the overhead data portion of a frame includes a pointer, the pointer indicating a start of a Synchronous Payload Envelope (SPE) that is not aligned to a first byte of the frame;

wherein the cell-packets are re-ordered based on the packetization order within the frame;

wherein the cell-packets are transmitted from the egress port using the clock pulse whereby the pointer and the SPE remain unchanged on the SONET frame at the egress port.

13. The skew-tolerant distributed network switch of claim 10 wherein the overhead data portion of a frame includes a pointer, the pointer indicating a start of a Synchronous Payload Envelope (SPE) that is not aligned to a first byte of the frame;

wherein the cell-packets are re-ordered based on the packetization order within the frame;

wherein the cell-packets are transmitted from the egress port using the clock pulse;

wherein the egress ports adjust the pointer by a common amount,

whereby the SPE is shifted by a common amount for all egress ports.

14. The skew-tolerant distributed network switch of claim 13 further comprising:

an offset clock pulse, having a same frequency as the clock pulse but also having a phase offset from the clock pulse;

wherein the frame is a SONET frame;

wherein the overhead data portion of the SONET frame has a pointer that points to the first byte of the SPE;

wherein the pointer is further adjusted at the ingress port by an amount equal to the phase offset between the clock pulse and the offset clock pulse,

whereby the pointer requires no further adjustment at the egress port.

15. The skew-tolerant distributed network switch of claim 7 wherein an amount of time to packetize one cell-packet in the input buffer is greater than any skews for the clock pulse to any network interface port.

16. The skew-tolerant distributed network switch of claim 7 wherein the cell-packet contains either overhead portion data or payload data portion data of a frame, but not data from both portions;

wherein cell-packets for the overhead data portions are re-ordered separately from the cell-packets for the payload data portion.

17. The skew-tolerant distributed network switch of claim 16 wherein the payload data portion and bytes of the overhead data portion that contain a pointer are formed into cell-packets,

wherein unnecessary overhead bytes are not formed into cell-packets and injected into the switch fabric.

18. A method for switching data streams in a network switch having clock skews comprising:

at an ingress port to the network switch,

receiving a data stream divided into frames synchronized to a sync pulse;

accumulating a first data packet of a frame of the data stream into an input buffer;

determining a destination address for the data stream, the destination address being an internal address of a switch node coupled to an egress port of the network switch;

generating an internal header that contains the destination address and a sequence number that indicates the first data packet of the frame;

attaching the internal header to the first data packet of the frame to form a first cell-packet;

injecting the first cell-packet into a switch fabric at the network switch;

(a) accumulating a next data packet of the frame into the input buffer;

(b) generating a next internal header that contains the destination address and a sequence number that indicates the next data packet of the frame;

(c) attaching the next internal header to the next data packet of the frame to form a next cell-packet;

(d) injecting the next cell-packet into a switch fabric at the network switch;

repeating (a) to (d) for all next data packets in the frame;

routing the first cell-packet and the next cell-packets through the switch fabric to an egress port using the destination address in the internal headers;

at the egress port,

receiving cell-packets from the switch fabric in any order;

reading the sequence number from the internal header of each cell-packet received;

accumulating in an output buffer data packets extracted from the cell-packets wherein the sequence number from the internal header is used to re-order the data packets from the cell-packets;

waiting for a next sync pulse to be received at the egress port to indicate a start of a next frame;

wherein the period of the sync pulse is greater than the sum of clock skew and cell-packet transmission latency from the ingress port to the egress port;

when the next sync pulse is received at the egress port, transmitting over an external link the first data packet from the output buffer; and

when the first data packet has been transmitted, transmitting over the external link the next data packet from the output buffer and transmitting other next data packets for the frame in an order determined by the sequence numbers from the internal headers;

whereby skews of the network switch are eliminated.

19. The method of claim 18 wherein the data streams are Synchronous Optical NETwork (SONET) data streams and the frame is an STS-1 frame or a plurality of STS-1 frames interleaved together.

20. The method of claim 19 wherein the data packets are data rows of an STS-1 frame.

21. The method of claim 19 further comprising:

at the ingress port, once the first data packet has been accumulated for a first STS-1 frame,

(f) accumulating an interleaved data packet of an interleaved STS-1 frame of the data stream into an input buffer,

(g) generating an internal header that contains the destination address and a sequence number that indicates the first data packet of the frame and an interleave number that indicates the interleaved data packet;

(g) attaching the internal header to the interleaved data packet to form a cell-packet;

(i) injecting the cell-packet into a switch fabric at the network switch; and

repeating (f)-(i) for other interleaved data packets before accumulating the next data packet of the first STS-1 frame,

whereby frames are dis-interleaved before being formed into cell-packets.

22. The method of claim 21 further comprising:

at the egress port,

using the interleave number and the sequence number to re-order cell-packets received at the egress port,

whereby data packets and frame interleaves are re-ordered for transmission over the external link.

23. The method of claim 22 wherein the data streams are concatenated SONET data streams;

wherein concatenated frames of the concatenated SONET data stream are dis-interleaved at the ingress port so as to create virtual STS-1 frames; and

wherein the virtual STS-1 frames are formed into data packets and injected into the switch fabric,

whereby the data packets are re-ordered at the egress port to recreate the concatenated SONET data stream.

24. The method of claim 20 wherein the first cell-packet is formed from Synchronous Payload Envelop (SPE) data, the SPE data packet starting at a location indicated by a pointer, the pointer being a SONET header pointer value;

wherein the first cell-packet is injected into the switch fabric after the first sync pulse occurring after the cell-packet is formed,

wherein the pointer at the egress port is set to a pre-determined value;

wherein the data packets are re-ordered at the egress port starting at the location within the SONET frame that was specified by the pre-determined value of the pointer;

whereby the pointer needs no further adjustment at the egress port.

25. The method of claim 19 wherein determining the destination address comprises accessing an internal routing table.

26. A Synchronous Optical NETwork (SONET) network switch comprising:

ingress ports, coupled to receive input data streams from external sources;

wherein the input data streams are segmented into SONET frames, each SONET frame having a header containing a pointer with a value that indicates a location of a start of a SONET Synchronous Payload Envelop (SPE) within the SONET frame;

egress ports, coupled to transmit data streams over external links;

switch means, coupled together and to the ingress and egress ports, to form a switch fabric, for switching cell-packets from an ingress port to an egress port;

the ingress ports, egress ports, and switch means receiving a synchronization clock pulse,

wherein different the synchronization clock pulse is received with varying skews at the ingress and egress ports;

an ingress port having;

link means for receiving a data stream divided into SONET frames and for synchronizing the frames to the synchronization clock pulse by first aligning the pointer to the synchronization pulse;

buffer means for accumulating a first data packet of a SONET frame of the data stream;

header means for generating an internal header that contains an internal destination means for indicating an egress port and sequence means for indicating a sequence order for the first data packet of the SONET frame;

packet means for attaching the internal header to the first data packet of the SONET frame to form a cell-packet;

packet injection means, coupled to the packet means, for injecting the first cell-packet into a switch fabric at the network switch;

wherein the buffer means accumulates other data packets after the first data packet, the header means generates a sequence number indicating an order for the data packet within the SONET frame, and the packet means forms other cell-packets containing the other data packets, the other packets injected into the switch fabric by the packet injection means;

the egress port having;

output buffer means, coupled to the switch means in the switch fabric, for receiving cell-packets from the switch fabric in any order;

re-order means, coupled to the output buffer means, for reading the sequence means from the internal header of each cell-packet received, and for re-ordering the data packets from the cell-packets in an order indicated by the sequence means;

delayed transmit means, coupled to receive the synchronization clock pulse, for waiting for a next synchronization clock pulse to be received at the egress port before transmitting over an external link a first re-ordered data from the output buffer means; and

continuous transmit means, coupled to the delayed transmit means, and triggered when the first re-ordered data has been transmitted, for transmitting over the external link a next re-ordered data from the output buffer means and transmitting other next re-ordered data for the SONET frame in an order determined by the sequence means;

wherein the cell-packets from a SONET frame are formed and injected into the switch fabric after a first synchronization clock pulse is received by the ingress port, but before the next synchronization clock pulse is received by the ingress port;

wherein the cell-packets are received by the egress port before the next synchronization clock pulse;

wherein the next synchronization clock pulse is a next pulse after the first synchronization clock pulse,

whereby the cell-packets are formed and routed through the switch fabric within one clock period and whereby SONET frames are transmitted out the egress port at the next synchronization clock pulse without changing the pointer value after the initial alignment.