Methods and systems for predicting IC chip yield

• US 6,751,519 B1
• Filed: 10/24/2002
• Issued: 06/15/2004
• Est. Priority Date: 10/25/2001
• Status: Expired due to Term

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Satya, Akella V. S., Song, Li, Weiner, Kurt H., Long, Robert Thomas
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): CABRERA, ZOILA E
• Application Number:
  US10/281,433
• Time in Patent Office: 600 Days
• Field of Search: 700/121, 700/108-110, 700/117, 702/182-184
• US Class Current: 700/121
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Disclosed are methods and apparatus for efficiently managing IC chip yield learning. In general terms, as each wafer lot moves through fabrication, yield information is obtained from each set of test structures for a particular process or defect mechanism. The nature of the yield information is such that it may be used directly or indirectly to predict product wafer test yield. In one implementation, the yield information includes a systematic yield (Y₀), a defect density (DD), and a defect clustering factor (α) determined based on the inspected test structure'"'"'s yield. A running average of the yield information for each process or defect mechanism is maintained as each wafer lot is processed. As a particular wafer lot moves through the various processes, a product wafer-sort test yield may be predicted at any stage in the fabrication process based on the running-average yield information maintained for previously fabricated wafer lots.

Claims

1. A method of managing and predicting product yield for a plurality of semiconductor products, comprising:

after a first process is performed on a particular semiconductor product, inspecting one or more test structures for the first process to obtain yield information related to a test structure yield for the first process, wherein a subsequent process remains to be performed on the particular semiconductor product; and

predicting a product yield of the semiconductor product at a time of fabrication completion, wherein the prediction is dynamically determined by combining the obtained yield information for the first process with at least an average of yield information obtained from a plurality of times for which the subsequent process was previously performed on a plurality of previously fabricated semiconductor products.

2. A method as recited in claim 1, wherein the semiconductor product is a product wafer lot and the predicted product yield is a predicted product wafer test yield.

3. A method as recited in claim 1, wherein the yield information includes a systematic yield and a defect density.

4. A method as recited in claim 1, wherein the yield information includes a systematic yield, a defect density, and a defect cluster factor α

.

5. A method as recited in claim 1, further comprising:

a) determining whether an excursion has occurred based on the predicted product yield;

b) when it is determined that an excursion has occurred, executing an excursion plan; and

c) when it is determined that an excursion has not occurred, performing a next process on the semiconductor product.

6. A method as recited in claim 5, further comprising:

d) after the next process is performed on the semiconductor product, inspecting one or more test structures for the next process to obtain yield information related to a test structure yield for the next process; and

e) predicting the product yield of the semiconductor product at a time of fabrication completion for the semiconductor product, wherein the prediction is dynamically based on the obtained yield information for the first and next process for the semiconductor product and an average of yield information for any remaining process(es) for the semiconductor product from previously fabricated semiconductor products.

7. A method as recited in claim 5, further comprising:

repeating operations (a) through (e) until a final process for the semiconductor product is completed;

after the final process for the semiconductor product has completed, performing an actual final test yield on the semiconductor product; and

after each process for the semiconductor product completes, updating an average of the yield information for the each process.

8. A method as recited in claim 7, wherein the update is accomplished after the final process for the semiconductor product has completed.

9. A method as recited in claim 7, wherein it is determined that an excursion has occurred when the predicted product yield differs by more than three standard deviations from an average predicted product yield for previously completed semiconductor products.

10. A method as recited in claim 7, wherein the excursion plan includes reworking the semiconductor product.

11. A method as recited in claim 7, wherein the excursion plan includes halting processing of the semiconductor product.

12. A method as recited in claim 7, wherein the excursion plan includes adjusting a process condition at the appropriate process step.

13. A method as recited in claim 1, wherein the one or more test structures are voltage contrast test structures which are designed for detection of systematic and random defects, such as electrical opens and shorts.

14. A method as recited in claim 13, wherein the inspection of the one or more test structures is accomplished with a scanning electron microscope or electron beam inspection tool.

15. A method as recited in claim 13, wherein the inspection of the one or more test structures is accomplished with an optical inspection tool.

16. A computer program product for managing and predicting product yield for a plurality of semiconductor products, the computer program product comprising:

at least one computer readable medium;

computer program instructions stored within the at least one computer readable product configured to;

after a first process is performed on a particular semiconductor product, receive yield information related to a test structure yield for the first process, wherein a subsequent process remains to be performed on the particular semiconductor product; and

predict a product yield of the semiconductor product at a time of fabrication completion, wherein the prediction is dynamically determined by combining the obtained yield information for the first process with at least an average of yield information obtained from a plurality of times for which the subsequent process was previously performed on a plurality of previously fabricated semiconductor products.

17. A computer program product as recited in claim 16, wherein the semiconductor product is a product wafer lot and the predicted product yield is a predicted product wafer test yield.

18. A computer program product as recited in claim 16, wherein the yield information includes a systematic yield and a defect density.

19. A computer program product as recited in claim 16, wherein the yield information includes a systematic yield, a defect density, and a defect cluster factor α

.

20. A computer program product as recited in claim 16, the computer program instructions stored within the at least one computer readable product being further configured to:

a) determine whether an excursion for the semiconductor product has occurred based on the predicted product yield;

b) when it is determined that an excursion for the semiconductor product has occurred, indicate that an excursion plan is to be executed; and

c) when it is determined that an excursion for the semiconductor product has not occurred, indicating that a next process on the semiconductor product is to be performed.

21. A computer program product as recited in claim 20, the computer program instructions stored within the at least one computer readable product being further configured to:

d) after the next process is performed on the semiconductor product, receive yield information related to a test structure yield for the next process; and

e) predict the product yield of the semiconductor product at a time of fabrication completion, wherein the prediction is dynamically based on the obtained yield information for the first and next process for the semiconductor product and an average of yield information for any remaining process(es) for the semiconductor product from previously fabricated semiconductor products.

22. A computer program product as recited in claim 20, the computer program instructions stored within the at least one computer readable product being further configured to:

repeat operations (a) through (e) until a final process is completed;

after each process for the semiconductor product completes, updating an average of the yield information for the each process.

23. A computer program product as recited in claim 22, wherein the update is accomplished after the final process for the semiconductor product has completed.

24. A computer program product as recited in claim 22, wherein it is determined that an excursion for the semiconductor product has occurred when the predicted product yield differs by more than three standard deviations from an average predicted product yield for previously completed semiconductor products.

25. A yield management system for managing and predicting product yield for a plurality of semiconductor products, the system comprising:

one or more processors;

one or more memory, wherein at least one of the processors and memory are adapted to;

after a first process is performed on a particular semiconductor product, receive yield information related to a test structure yield for the first process, wherein a subsequent process remains to be performed on the particular semiconductor product; and

predict a product yield of the semiconductor product at a time of fabrication completion, wherein the prediction is dynamically determined by combining the obtained yield information for the first process with at least an average of yield information obtained from a plurality of times for which the subsequent process was previously performed on a plurality of previously fabricated semiconductor products.

26. A yield management system as recited in claim 25, wherein the semiconductor product is a product wafer lot and the predicted product yield is a predicted product wafer test yield.

27. A yield management system as recited in claim 25, wherein the yield information includes a systematic yield and a defect density.

28. A yield management system as recited in claim 25, wherein the yield information includes a systematic yield, a defect density, and a defect cluster factor α

.

29. A yield management system as recited in claim 25, wherein the at least one of the processors and memory are further adapted to:

a) determine whether an excursion for the semiconductor product has occurred based on the predicted product yield;

b) when it is determined that an excursion for the semiconductor product has occurred, indicate that an excursion plan is to be executed; and

c) when it is determined that an excursion has not occurred, indicating that a next process on the semiconductor product is to be performed.

30. A yield management system as recited in claim 29, wherein the at least one of the processors and memory are further adapted to:

d) after the next process is performed on the semiconductor product, receive yield information related to a test structure yield for the next process; and

e) predict the product yield of the semiconductor product at a time of fabrication completion, wherein the prediction is dynamically based on the obtained yield information for the first and next process for the semiconductor product and an average of yield information for any remaining process(es) for the semiconductor product from previously fabricated semiconductor products.

31. A yield management system as recited in claim 29, wherein the at least one of the processors and memory are further adapted to:

repeat operations (a) through (e) until a final process is completed;

after each process for the semiconductor product completes, updating an average of the yield information for the each process.

32. A yield management system as recited in claim 31, wherein the update is accomplished after the final process for the semiconductor product has completed.

33. A yield management system as recited in claim 31, wherein it is determined that an excursion for the semiconductor product has occurred when the predicted product yield differs by more than three standard deviations from an average predicted product yield for previously completed semiconductor products.