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Method of scaling table based cell library timing models in order to take into account process, temperature and power supply

  • US 6,751,579 B1
  • Filed: 03/09/1999
  • Issued: 06/15/2004
  • Est. Priority Date: 03/09/1999
  • Status: Expired due to Fees
First Claim
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1. A method for producing a logic cell, the method comprising the following steps:

  • (a) generating a timing model for the logic cell, including the following substeps;

    (a.1) selecting output load indices (Load1, Load2, . . . ,Loadm) which specify output load for the first logic cell, (a.2) selecting input ramp indices (IR1, IR2, . . . ,IRn) which specify input ramp for the first logic cell, (a.3) generating baseline output ramp values (ORbl [j,k]) for each output load index (Loadj) and input ramp index (IRk) pair, (a.4) scaling the output load indices by a first scaling factor (λ

    ), (a.5) scaling the input ramp indices by a second scaling factor (ρ

    ), and (a.6) generating scaled output ramp values (ORscaled [j,k]) for each scaled output load index and scaled input ramp index pair, wherein a numerical value of ORscaled [j, k] represents a value of output ramp at new Process, Power supply, Temperature conditions when the output load for the first logic cell is equal to λ

    *Loadj and the input ramp for the first logic cell is equal to ρ

    *IRk; and

    , (b) building the logic cell based on the timing model generated in step (a).

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