Method of scaling table based cell library timing models in order to take into account process, temperature and power supply

• US 6,751,579 B1
• Filed: 03/09/1999
• Issued: 06/15/2004
• Est. Priority Date: 03/09/1999
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Findley, Paul R., Misheloff, Michael N.
• Primary Examiner(s): JONES, HUGH M
• Application Number:
  US09/264,770
• Time in Patent Office: 1,925 Days
• Field of Search: 703/2
• US Class Current: 703/2
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method is presented for generating a timing model for a logic cell. Output load indices (Load₁, Load₂, . . . ,Load_m) are selected which specify output load for the first logic cell. Input ramp indices (IR₁, IR₂, . . . ,IR_n) are selected which specify input ramp for the first logic cell. Baseline output ramp values (OR_bl [j,k]) are generated for each output load index (Load_j) and input ramp index (IR_k) pair. In order to take into account process, power and temperature variations, scaling factors are used to scale the indices. For example these scaling factors can be utilized for many different logic cells in a cell library. In one embodiment, the output load indices are scaled by a first scaling factor (λ). The input ramp indices are scaled by a second scaling factor (ρ). Scaled output ramp values (OR_scaled [j,k]) are generated for each scaled output load index and scaled input ramp index pair. A third scaling factor (γ) is used to generate the scaled output ramp values (OR_scaled [j,k]). Additionally, delay values can be generated as well. Specifically, baseline delay values (Delay_bl [j, k]) are generated for each output load index (Load_j) and input ramp index (IR_k) pair. Scaled delay values (Delay_scaled [j, k]) are generated for each scaled output load index and scaled input ramp index pair.

Claims

1. A method for producing a logic cell, the method comprising the following steps:

(a) generating a timing model for the logic cell, including the following substeps;

(a.1) selecting output load indices (Load₁, Load₂, . . . ,Load_m) which specify output load for the first logic cell,

(a.2) selecting input ramp indices (IR₁, IR₂, . . . ,IR_n) which specify input ramp for the first logic cell,

(a.3) generating baseline output ramp values (OR_bl [j,k]) for each output load index (Load_j) and input ramp index (IR_k) pair,

(a.4) scaling the output load indices by a first scaling factor (λ

),

(a.5) scaling the input ramp indices by a second scaling factor (ρ

), and

(a.6) generating scaled output ramp values (OR_scaled [j,k]) for each scaled output load index and scaled input ramp index pair, wherein a numerical value of OR_scaled [j, k] represents a value of output ramp at new Process, Power supply, Temperature conditions when the output load for the first logic cell is equal to λ

*Load_j and the input ramp for the first logic cell is equal to ρ

*IR_k; and

,

(b) building the logic cell based on the timing model generated in step (a).

2. A method as in claim 1 wherein substep (a.6) includes using a third scaling factor (γ

) to generate the scaled output ramp values (OR_scaled [j,k]), using the following equation;

3. A method as in claim 2 wherein baseline output ramp value at zero load and minimum input ramp (OR_bl [0,1]) is approximated using the following equation:

4. A method as in claim 1 wherein substep (a.6) includes using a third scaling factor (γ

) to generate the scaled output ramp as a function of output load and input ramp OR_scaled(Output Load, Input ramp) in accordance with the following equation;

5. A method as in claim 4 wherein baseline output ramp value at zero load and minimum input ramp (OR_bl [0,1]) is approximated using the following equation:

6. A method as in claim 1 wherein substep (a.6), includes using a third scaling factor (γ

) to generate the scaled output ramp values (OR_scaled [j,k]).

7. A method as in claim 6 wherein a value of the first scaling factor varies dependent upon process, power and temperature variances, wherein a value of the second scaling factor also varies dependent upon process, power and temperature variance, and wherein a value of the third scaling factor also varies dependent upon process, power and temperature variance.

8. A method as in claim 7 wherein the value of the first scaling factor additionally varies based on whether voltage at an output node of the logic cell is rising or falling, wherein the value of the second scaling factor also varies based on whether voltage at the output node of the logic cell is rising or falling, and wherein the value of the third scaling factor also varies based on whether voltage at the output node of the logic cell is rising or falling.

9. A method as in claim 1 wherein step (a) additionally comprises the following substeps:

(a.7) generating baseline delay values (Delay_bl [j, k]) for each output load index (Load_j) and input ramp index (IR_k) pair; and

,

(a.8) generating scaled delay values (Delay_scaled [j, k]) for each scaled output load index and scaled input ramp index pair.

10. A method as in claim 9 wherein:

substep (a.8) includes the following substeps;

generating new values (Dt0_bl [j, k]) for each output load index (Load_j) and input ramp index (IR_k) pair based on the baseline delay values (Delay_bl [j, k]), the baseline output ramp values (OR_bl [j,k]), and a factor (φ

) which takes into account non-linearity of voltage waveforms within the logic cell, in accordance with the following equation;

11. A method as in claim 10 wherein baseline new value at zero load and zero input ramp (Dt0_bl [0, 0]) is approximated using the following equation:

12. A method as in claim 9 wherein substep (a.8) includes the following substeps:

generating new values (Dt0_bl [j, k]) for each output load index (Load_j) and input ramp index (IR_k) pair based on the baseline delay values (Delay_bl [j, k]), the baseline output ramp values (OR_bl [j,k]), and a factor (φ

) which takes into account non-linearity of voltage waveforms within the logic cell, in accordance with the following equation;

13. A method as in claim 12 wherein baseline output ramp value at zero load and minimum input ramp (OR_bl [0,1]) is approximated using the following equation:

14. A method for producing a logic cell, the method comprising the following steps:

(a) generating a timing model for the logic cell, including the following substeps;

(a.1) selecting output load indices (Load₁, Load₂, . . . ,Load_m) which specify output load for the first logic cell,

(a.2) selecting input ramp indices (IR₁, IR₂, . . . ,IR_n) which specify input ramp for the first logic cell,

(a.3) generating baseline delay values (Delay_bl [j, k]) for each output load index (Load_j) and input ramp index (IR_k) pair,

(a.4) scaling the output load indices by a first scaling factor (λ

),

(a.5) scaling the input ramp indices by a second scaling factor (ρ

), and

(a.6) generating scaled delay values (Delay_scaled [j, k]) for each scaled output load index and scaled input ramp index pair, wherein a numerical value of Delay_scaled [j, k] represents a value of transition delay at new Process, Power supply, Temperature conditions when the output load for the first logic cell is equal to λ

*Load_j and the input ramp for the first logic cell is equal to ρ

*IR_k; and

,

(b) building the logic cell based on the timing model generated in step (a).

15. A method as in claim 14 wherein substep (a.6) includes the following substeps:

generating baseline output ramp values (OR_bl [j,k]) for each output load index (Load_j) and input ramp index (IR_k) pair;

generating new values (Dt0_bl [j, k]) for each output load index (Load_j) and input ramp index (IR_k) pair based on the baseline delay values (Delay_bl [j, k]), the baseline output ramp values (OR_bl [j,k]), and a factor (φ

) which takes into account non-linearity of voltage waveforms within the logic cell, in accordance with the following equation;

16. A method as in claim 15 wherein baseline new value at zero load and zero input ramp (Dt0_bl [0, 0]) is approximated using the following equation:

17. A method as in claim 14 wherein substep (a.6) includes the following substeps:

generating baseline output ramp values (OR_bl [j,k]) for each output load index (Load_j) and input ramp index (IR_k) pair;

generating new values (Dt0_bl [j, k]) for each output load index (Load_j) and input ramp index (IR_k) pair based on the baseline delay values (Delay_bl [j, k]), the baseline output ramp values (OR_bl [j,k]), and a factor (φ

) which takes into account non-linearity of voltage waveforms within the logic cell, in accordance with the following equation;

18. A method as in claim 17 wherein baseline output ramp value at zero load and minimum input ramp (OR_bl [0,1]) is approximated using the following equation:

19. A method as in claim 14 wherein substep (a.6) includes using a third scaling factor (α

) to generate the scaled delay values (Delay_scaled [j,k]).

20. A method as in claim 19 wherein a value of the first scaling factor varies dependent upon process, power and temperature variances, wherein a value of the second scaling factor also varies dependent upon process, power and temperature variance, and wherein a value of the third scaling factor also varies dependent upon process, power and temperature variance.

21. A method as in claim 20 wherein the value of the first scaling factor additionally varies based on whether voltage at an output node of the logic cell is rising or falling, wherein the value of the second scaling factor also varies based on whether voltage at the output node of the logic cell is rising or falling, and wherein the value of the third scaling factor does not vary based on whether voltage at the output node of the logic cell is rising or falling.