Memory device having a programmable register

• US 6,751,696 B2
• Filed: 04/13/2001
• Issued: 06/15/2004
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/835,263
• Publication Number:
  US 20010023466A1
• Time in Patent Office: 1,159 Days
• Field of Search: 710/100, 710/305, 365/233, 365/189.01, 365/189.04, 365/189.05, 365/194
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 : Control signal input circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Claims

1. A synchronous memory device including an array of memory cells, the synchronous memory device comprises:

clock receiver circuitry to receive an external clock signal;

input receiver circuitry to sample a first operation code in response to a rising edge transition of the external clock signal;

a programmable register to store a value which is representative of an amount of time to transpire before the memory device outputs data, wherein the memory device stores the value in the programmable register in response to the first operation code; and

output driver circuitry to output data in response to a second operation code, wherein the data is output after the amount of time transpires, and wherein;

the output driver circuitry outputs a first portion of the data synchronously with respect to a rising edge transition of the external clock signal and outputs a second portion of the data synchronously with respect to a falling edge transition of the external clock signal.

2. The memory device of claim 1 wherein the first operation code is included in a control register access packet.

3. The memory device of claim 2 wherein the first operation code and the value are included in the same control register access packet.

4. The memory device of claim 1 wherein the memory device is a synchronous dynamic random access memory.

5. The memory device of claim 1 wherein the input receiver circuitry receives the second operation code and address information.

6. The memory device of claim 5 wherein the input receiver circuitry receives the second operation code and the address information on consecutive clock cycles of the external clock signal.

7. The memory device of claim 1 wherein the amount of time is a number of clock cycles of the external clock signal.

8. The memory device of claim 1 wherein the input receiver circuitry receives a third operation code, wherein the third operation code initiates a write operation in the memory device.

9. The memory device of claim 8 wherein the input receiver circuitry receives the third operation code and address information.

10. The memory device of claim 1 further including delay lock loop circuitry coupled to the clock receiver circuitry to generate a first internal clock signal, wherein the data is output in response to the first internal clock signal.

11. The memory device of claim 1 wherein the output driver circuitry outputs the data onto a bus.

12. The memory device of claim 11 wherein the bus includes a set of signal lines to carry multiplexed address information, data and control information.

13. A method of operation of a synchronous memory device, wherein the memory device includes an array of memory cells and a programmable register, the method of operation of the memory device comprises:

sampling a first operation code synchronously with respect to an external clock signal;

receiving a binary value that is representative of an amount of time to transpire before the memory device outputs data in response to a second operation code, wherein the memory device stores the binary value in the programmable register in response to the first operation code;

sampling the second operation code; and

outputting the data after the amount of time transpires, wherein a first portion of the data is output synchronously with respect to a first transition of the external clock signal and a second portion of the data is output synchronously with respect to a second transition of the external clock signal.

14. The method of claim 13 wherein the second operation code is sampled synchronously with respect to the external clock signal.

15. The method of claim 13 wherein the binary value is representative of a number of clock cycles of the external clock signal.

16. The method of claim 15 further including:

receiving block size information, wherein the block size information defines an amount of data to be output in response to the second operation code, wherein the memory device outputs the amount of data after the number of clock cycles of the external clock signal transpire.

17. The method of claim 13 further including receiving address information synchronously with respect to the external clock signal.

18. The method of claim 17 wherein the address information and the second operation code are included in a read request packet.

19. The method of claim 13 further including receiving precharge information.

20. The method of claim 19 wherein the precharge information includes a binary bit, wherein, after accessing the data from the array of memory cells, the memory device retains contents of a plurality of sense amplifiers for a subsequent memory operation as a result of a first state of the binary bit.

21. The method of claim 13 wherein the first transition of the external clock signal is a rising edge transition and the second transition of the external clock signal is a falling edge transition.

22. The method of claim 21 wherein the first and second transitions of the external clock signal are consecutive transitions of the external clock signal.

23. The method of claim 13 wherein the first operation code is sampled during an initialization sequence after power is applied to the memory device.

24. The method of claim 13 wherein the memory device outputs the data onto an external bus.

25. The method of claim 24 wherein the external bus includes a set of signal lines to carry multiplexed address information, data and control information.

26. A method of controlling a synchronous memory device by a memory controller, wherein the memory device includes an array of memory cells and a programmable register, the method of controlling the memory device comprises:

providing a first operation code to the memory device, wherein the first operation code initiates an access of the programmable register in the memory device in order to store a binary value;

providing the binary value to the memory device, wherein the memory device stores the binary value in the programmable register in response to the first operation code;

providing a second operation code to the memory device, wherein the second operation code instructs the memory device to accept data that is issued by the memory controller;

providing a first portion of the data to the memory device in response to a rising edge transition of the external clock signal; and

providing a second portion of the data to the memory device in response to a falling edge transition of the external clock signal.

27. The method of claim 26 wherein the binary value is representative of a delay time to transpire before the memory device samples the data, and wherein the first portion of the data is provided to the memory device after the delay time transpires.

28. The method of claim 26 wherein the binary value is representative of a number of clock cycles of the external clock signal to transpire before the memory device samples the data, and wherein the first portion of the data is provided to the memory device after the number of clock cycles transpire.

29. The method of claim 26 wherein the binary value is representative of a delay time to transpire before the memory device outputs data in response to an operation code which instructs the memory device to output data.

30. The method of claim 26 further including:

providing block size information to the memory device, wherein the block size information defines an amount of data to be accepted by the memory device in response to the second operation code.

31. The method of claim 26 further including providing address information to the memory device.

32. The method of claim 31 wherein the address information and the second operation code are included in a write request packet.

33. The method of claim 26 wherein the first operation code and the data are provided to the memory device via an external bus.

34. The method of claim 33 wherein the external bus includes a set of signal lines used to carry multiplexed address information, the data and control information.

35. The method of claim 26 wherein the second operation code includes precharge information.

36. A synchronous memory device, wherein the memory device includes an array of memory cells, the memory device comprises:

input receiver circuitry to sample a first operation code in response to a first transition of an external clock signal;

a programmable register to store a binary value in response to the first operation code, wherein the binary value is representative of an amount of time to transpire before the memory device outputs data; and

output driver circuitry to output data in response to a second operation code and after the amount of time transpires, wherein a first portion of the data is output in response to a second transition of the external clock signal and a second portion of the data is output in response to a third transition of the external clock signal.

37. The memory device of claim 36 wherein the binary value is representative of a number of clock cycles of the external clock signal.

38. The memory device of claim 36 wherein the second transition of the external clock signal is a rising edge transition and the third transition of the external clock signal is a falling edge transition.

39. The memory device of claim 38 wherein the second and third transitions of the external clock signal are consecutive transitions.

40. The memory device of claim 39 wherein the first operation code and the binary value are included in a packet.

41. The memory device of claim 40 wherein the first operation code and the binary value are included in the same packet.

42. The memory device of claim 36 further including delay lock loop circuitry to generate a first internal clock signal, wherein the data is output in response to the first internal clock signal.

43. The memory device of claim 36 wherein the input receiver circuitry receives address information.

44. The memory device of claim 36 wherein the output driver circuitry outputs the data onto an external bus having a set of signal lines used to carry multiplexed address information, the data and control information.

45. The memory device of claim 44 wherein the input receiver circuitry samples the first operation code from the external bus.

46. The memory device of claim 36 wherein the output driver circuitry and the input receiver circuitry are connected to a common pad.

47. The memory device of claim 36 wherein the memory device is a synchronous dynamic random access memory.

48. A synchronous memory device including an array of memory cells, wherein the memory device comprises:

a programmable register to store a binary value;

a plurality of input receivers to sample first and second operation codes synchronously with respect to an external clock signal, wherein;

the first operation code initiates storage of the binary value in the programmable register; and

the second operation code initiates a read operation; and

a plurality of output drivers to output data in response to the second operation code, wherein;

a first portion of the data is output synchronously with respect to a rising edge transition of the external clock signal; and

a second portion of the data is output synchronously with respect to a falling edge transition of the external clock signal.

49. The memory device of claim 48 wherein the first operation code is sampled synchronously with respect to a first transition of the external clock signal and the second operation code is sampled synchronously with respect to a second transition of the external clock signal.

50. The memory device of claim 49 wherein the first operation code is included in a control register access packet and the second operation code is included in a read request packet.

51. The memory device of claim 50 wherein the read request packet includes address information.

52. The memory device of claim 48 wherein the array of memory cells includes dynamic memory cells.

53. The memory device of claim 52 wherein the memory device further includes a delay lock loop, coupled to the plurality of output drivers, to synchronize the outputting of data with the external clock signal.

54. The memory device of claim 53 wherein the delay lock loop further includes:

a delay line to generate an internal clock signal, wherein the internal clock signal has a delay with respect to the external clock signal; and

a comparator to compare the internal clock signal with the external clock signal, wherein the delay of the internal clock signal is adjusted based on the comparison between the internal clock signal and the external clock signal.

55. The memory device of claim 48 wherein the second operation code includes precharge information.

56. The memory device of claim 55 further including a plurality of sense amplifiers to access the data from the array of memory cells, wherein the precharge information initiates automatic precharge of the plurality of sense amplifiers after the data is accessed from the array of memory cells.

57. The memory device of claim 48 wherein the binary value represents a device identifier.

58. The memory device of claim 48 wherein the binary value represents a location of a defective portion of the array of memory cells.

59. The memory device of claim 48 wherein the binary value represents a delay time.

60. The memory device of claim 59 wherein the first portion of data is output, in response to the second operation code, after the delay time transpires.