Field programmable gate array and microcontroller system-on-a-chip

• US 6,751,723 B1
• Filed: 09/02/2000
• Issued: 06/15/2004
• Est. Priority Date: 09/02/2000
• Status: Expired due to Term

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Hightower, David, Kundu, Arunangshu, Goldfein, Arnold, Plants, William C.
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/654,237
• Time in Patent Office: 1,382 Days
• Field of Search: 348/721, 348/719, 375/222, 712/10, 712/17, 712/18, 712/35, 712/36, 712/33, 712/11, 712/14, 712/13, 716/17, 716/16, 326/39, 326/41
• US Class Current: 712/36
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

An system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

Claims

1. An integrated circuit comprising:

a field programmable gate array (FPGA) core having logic clusters and static random access memory modules;

a FPGA virtual component interface translator coupled to the FPGA core and configured to translate signals from a first protocol to a second protocol;

a system bus coupled to the FPGA virtual component interface translator and configured to convey signals within the integrated circuit;

a microcontroller coupled to the system bus;

a microcontroller virtual component interface translator coupled to the microcontroller and the system bus and configured to receive a signal from the FPGA core in the second protocol and translate the signal into a third protocol for the microcontroller; and

programmable routing resources coupled to the FPGA core and to the microcontroller and configured to allow a plurality of programmable connections between the FPGA core and the microcontroller.

2. The integrated circuit of claim 1 wherein the plurality of programmable connections further comprise direct connections between the FPGA core and the microcontroller, and the integrated circuit is configurable to provide direct connections between the FPGA core and the microcontroller and connections between the FPGA core and the microcontroller through the FPGA virtual component interface and the microcontroller virtual component interface.

3. The integrated circuit of claim 2 further comprising a first plurality of signals directed between the FPGA core and the microcontroller exclusively through the FPGA core virtual component interface and the microcontroller virtual component interface.

4. The integrated circuit of claim 3 further comprising a second plurality of signals directed between the FPGA core and the microcontroller through either the FPGA core virtual component interface and the microcontroller virtual component interface or through the routing resources.

5. The integrated circuit of claim 4 further comprising a third plurality of signals directed between the FPGA core and the microcontroller exclusively through the routing resources.