Method of integrated circuit design checking using progressive individual network analysis

• US 6,751,744 B1
• Filed: 12/30/1999
• Issued: 06/15/2004
• Est. Priority Date: 12/30/1999
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Allen, Robert J., Cohn, John M., Hathaway, David J.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/475,799
• Time in Patent Office: 1,629 Days
• Field of Search: 713/40.1, 716/2, 716/6, 716/4, 716/1, 716/5, 716/10, 714/745, 703/17
• US Class Current: 713/401
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking

Abstract

A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network'"'"'s sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition is disclosed. The method, at each step, decides if a quick to calculate parameter provides sufficient design margin or if a more accurate but longer to calculate parameter is required.

Claims

1. A method of checking an integrated circuit network design comprising the steps of:

calculating a first performance parameter by analyzing said networks sensitivity to a signal applied to said network;

comparing said first performance parameter to at least one rule to determine a first pass condition and writing said first performance parameter to a netlist file in response to a pass to said first pass condition; and

calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing said second performance parameter to said netlist file in response to a pass to said second pass condition and writing an error flag to said netlist file in response to a fail to said second pass condition.

2. The method of claim 1, wherein said performance parameters are delays expressed in time, wire length or wire resistance, said rule is a timing rule, and said first network model is a network timing model.

3. The method of claim 1, wherein said performance parameters are voltage levels, said rule is a noise sensitivity rule and said first network model is a network noise sensitivity model.

4. The method of claim 1, wherein said performance parameters are current levels, said rule is a power consumption rule and said first network model is a network power consumption model.

5. A method of checking a integrated circuit network design comprising the steps of:

(a) providing a set of network models of increasing complexity;

(b) selecting the least complex network model from said set of models;

(c) applying a signal to said network based on said selected model to determine a performance parameter;

(d) comparing said performance parameter to a pass rule to determine a pass condition;

(e) in response to a pass to said pass condition writing said performance parameter to a netlist file and terminating said checking of said design;

(f) in response to fail condition selecting the next higher complexity model selected and repeating steps (b) through (e); and

(g) writing an error flag to said netlist file.

6. The method of claim 5, wherein said performance parameters are delays expressed in time, wire length or wire resistance, said pass rule is a timing rule, and said set of network models is comprised of timing models.

7. The method of claim 5, wherein said performance parameters are voltage levels, said pass rule is a noise sensitivity rule, and said set of network models is comprised of noise sensitivity models.

8. The method of claim 5, wherein said performance parameters are current levels said pass rule is a power consumption rule and said set of network models is comprised of power consumption models.

9. A method of checking a integrated circuit design comprised of a set of networks comprising the steps of:

(a) selecting and analyzing each network in turn by the steps of,

(i) calculating a first performance parameter by analyzing said selected networks sensitivity to a signal applied to said selected network;

(ii) comparing said first performance parameter to at least one rule to determine a first pass condition and writing said first performance parameter to a netlist file in response to a pass to said first pass condition; and

(iii) calculating a second performance parameter based on a first network model applied to said selected network to determine a second pass condition in response to a failure to said first pass condition and writing said second performance parameter to said netlist file in response to a pass to said second pass condition and writing an error flag to said netlist file in response to a fail to said second pass condition; and

(b) repeating steps (i) through (iii) until all said networks have been selected and analyzed.

10. The method of claim 9, wherein said performance parameters are delays expressed in time, wire length or wire resistance, said pass rule is a timing rule, and said set of network models is comprised of timing models.

11. The method of claim 9, wherein said performance parameters are voltage levels, said pass rule is a noise sensitivity rule, and said set of network models is comprised of noise sensitivity models.

12. The method of claim 9, wherein said performance parameters are current levels, said pass rule is a power consumption rule, and said set of network models is comprised of power consumption models.

13. A method of checking a integrated circuit design comprised of a set of networks comprising the steps of

(a) selecting and analyzing each network in turn by the steps of,

(i) providing a set of network models of increasing complexity;

(ii) selecting the least complex network model from said set of models;

(iii) applying a signal to said selected network based on said selected model to determine a performance parameter;

(iv) comparing said performance parameter to a pass rule to determine a pass condition;

(v) in response to a pass to said pass condition writing said performance parameter to a netlist file and terminating said checking of said design;

(vi) in response to fail condition selecting the next higher complexity mode selected and repeating steps (iii) through (v) until all models have then selected; and

(vii) writing an error flag to said netlist file; and

(b) repeating steps (iii) through (vii) until all said networks have been selected and analyzed.

14. The method of claim 13, wherein said performance parameters are delays expressed in time, wire length or wire resistance, said pass rule is a timing rule, and said set of network models is comprised of timing models.

15. The method of claim 13, wherein said performance parameters are voltage levels, said pass rule is a noise sensitivity rule, and said set of network models is comprised of noise sensitivity models.

16. The method of claim 13, wherein said performance parameters are current levels, said pass rule is a power consumption rule, and said set of network models is comprised of power consumption models.

17. A method of timing analysis for an integrated circuit design comprised of a set of networks comprising the steps of:

(a) selecting and analyzing each network in turn by the steps of;

(i) calculating a first network delay by subtracting said device only delays of said selected network from a preliminary timing requirement of said selected network;

(ii) comparing said first delay to at least one network delay rule to determine if said delay is below a threshold limit and said first delay being below said threshold limit, writing a zero delay to a netlist file and terminating analysis of said selected network;

(iii) in response to said first delay being above said threshold limit but below a screen limit, writing said first delay to said netlist file and terminating analysis of said selected network;

(iv) in response to said first delay being above said screen limit, determining if said first delay is above a maximum limit and if said first delay is above said maximum limit, writing an error flag to said netlist file and terminating analysis of said selected network;

(v) in response to said first delay being below said maximum limit, performing a network parasitic element extraction using a first delay model and calculating a second network delay;

(vi) comparing said second delay to said preliminary timing requirement to determine a pass condition and in response to a pass to said pass condition, writing said second delay to said netlist file and terminating analysis of said selected network;

(vii) in response to a fail to said pass condition, determining if said second delay is above said maximum limit and if said second delay is above said maximum limit writing an error flag to said netlist file and terminating analysis of said selected network;

(viii) in response to said second delay being below said maximum limit, performing a network parasitic element extraction using a second delay model and calculating a third network delay; and

(ix) comparing said third delay to said maximum limit and if said second delay is below said maximum limit writing said third delay to said netlist file otherwise writing an error flag to said netlist file and terminating analysis of said selected network; and

(b) repeating steps (i) through (ix) until all said networks have been selected and analyzed.

18. The method of claim 17 wherein said first delay model is less complex than said second delay model.

19. The method of claim 18 wherein said delays are calculated and expressed as wire lengths.

20. The method of claim 18 wherein said delays are calculated and expressed as wire resistance'"'"'s.

21. The method of claim 18 wherein said parasitics'"'"' of said first model are grounded capacitance'"'"'s and said parasitics of said second model are capacitance/resistance networks.

22. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for checking an integrated network circuit design comprising the steps of:

calculating a first performance parameter by analyzing said networks sensitivity to a signal applied to said network;

comparing said first performance parameter to at least one rule to determine a first pass condition and writing said first performance parameter to a netlist file in response to a pass to said first pass condition; and

calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing said second performance parameter to said netlist file in response to a pass to said second pass condition and writing an error flag to said netlist file in response to a fail to said second pass condition.

23. The method of claim 22, wherein said performance parameters are delays expressed in time, wire length or wire resistance, said rule is a tinting rule, and said first network model is a network timing model.

24. The method of claim 22, wherein said performance parameters are voltage levels, said rule is a noise sensitivity rule and said first network model is a network noise sensitivity model.

25. The method of claim 22, wherein said performance parameters are current levels, said rule is a power consumption rule and said first network model is a network power consumption model.

26. A computerized design system which checks an integrated circuit network design which comprises:

means for calculating a first performance parameter by analyzing said networks sensitivity to a signal applied to said network;

means for comparing said first performance parameter to at least one rule to determine a first pass condition and writing said first performance parameter to a netlist file in response to a pass to said first pass condition; and

means for calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing said second performance parameter to said netlist file in response to a pass to said second pass condition and writing an error flag to said netlist file in response to a fail to said second pass condition.

27. The method of claim 26, wherein said performance parameters are delays expressed in time, wire length or wire resistance, said rule is a tinting rule, and said first network model is a network timing model.

28. The method of claim 26, wherein said performance parameters are voltage levels, said rule is a noise sensitivity rule and said first network model is a network noise sensitivity model.

29. The method of claim 26, wherein said performance parameters are current levels, said rule is a power consumption rule and said first network model is a network power consumption model.