Universal multi-bus breakpoint unit for a configurable system-on-chip

• US 6,751,751 B1
• Filed: 11/06/2000
• Issued: 06/15/2004
• Est. Priority Date: 11/06/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Murray, James, Allegrucci, Jean-Didier
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US09/707,459
• Time in Patent Office: 1,317 Days
• Field of Search: 714/34, 714/39, 714/40, 714/43, 714/44, 714/47, 714/56, 714/37, 710/15, 710/17-19, 710/48, 710/49, 710/47
• US Class Current: 714/34
• CPC Class Codes: G06F 11/364 tracing values on a bus
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

The present invention provides a hardware breakpoint unit for a multibus, processor-based, configurable circuit. The multi-bus breakpoint unit connects to and allows tracing of multiple busses and includes the ability to break on the occurrence of a pre-determined bus event on any one of the multiple busses. The multi-bus breakpoint unit can be connected to and programmed by a host debugging system via a port on the target chip.

Claims

1. A device comprising:

a plurality of busses; and

a breakpoint unit with a configuration logic, the breakpoint unit coupled to the plurality of busses and able to break on the detection of a specified bus event occurring on a selected bus, where the specified bus event and the selected bus are set by the configuration logic.

2. The device of claim 1 further comprising:

an interface at which a host debugging system is coupled to the device.

3. The device of claim 2, wherein the interface complies with a JTAG standard.

4. The device of claim 1, further comprising:

a scratchpad RAM coupled to the breakpoint unit to store bus events occurring before and after a breakpoint event.

5. The device of claim 1, wherein the configuration logic is dynamically programmed with a second specified bus event after the breakpoint unit has detected occurrence of a first specified bus event.

6. An integrated circuit comprising:

a processor coupled to a local processor bus;

a programmable logic coupled to a peripheral bus; and

a programmable breakpoint unit with a configuration logic, the breakpoint unit coupled to the processor bus and the peripheral bus and able to break on the detection of a specified bus event on a selected bus, where the specified bus event and selected bus are set by the configuration logic.

7. The circuit of claim 6, further comprising:

an interface to receive a host debugging system.

8. The circuit of claim 7 wherein the interface complies with a JTAG standard.

9. The circuit of claim 6 wherein the configuration logic is dynamically programmed with a second specified bus event on a second selected bus after the breakpoint unit has detected the occurrence of a first specified bus event.

10. The circuit of claim 6 wherein the breakpoint unit is further comprises:

a bus select logic to select a bus from the local processor bus and the peripheral bus;

an event detection logic to detect an occurrence of a specified bus event on the selected bus by comparing bus data read on the selected bus with the specified bus event; and

a breakpoint controller logic to take control of the selected bus based on the detection of the specified bus event.

11. The circuit of claim 10, further comprising:

a mask logic to mask the selected bus data with a masking pattern before the bus data is compared to the specified bus event.

12. The circuit of claim 6, further comprising:

counters to track a number of occurrences of a breakpoint condition and to trigger the breakpoint controller unit after a preset number of the breakpoint conditions to declare a breakpoint event.

13. A breakpoint unit coupled to a plurality of busses comprising:

a bus select logic to select a bus from a plurality of busses;

a programmable configuration logic to configure the breakpoint unit to detect a specified bus event on the selected bus of the plurality of busses;

an event detection logic to detect an occurrence of the specified bus event on the selected bus by comparing bits of the selected bus with the specified bus event.

14. The breakpoint unit of claim 13, further comprising:

a breakpoint controller logic to take control of the selected bus based on the detection of the specified bus event.

15. The breakpoint unit of claim 13, wherein taking control of the selected bus comprises freezing a processor coupled to one of the plurality of busses.

16. The breakpoint unit of claim 13, further comprising:

a mask logic to mask the selected bus data with a masking pattern before the bus data is compared to the specified bus event.

17. The breakpoint unit of claim 13, further comprising:

a counter logic to count a number of times the specified breakpoint condition occurs.

18. The breakpoint unit of claim 17, wherein the counter logic includes multiple counters, each counter associated with a breakpoint condition and able to count the number of times the breakpoint condition occurs.

19. The breakpoint unit of claim 17, wherein a breakpoint event occurs when the counter reaches a preset number.

20. The breakpoint unit of claim 13 wherein the bus select logic has a plurality of bus interfaces at which the plurality of busses are coupled to the breakpoint unit.

21. The breakpoint unit of claim 13 where the configuration logic is comprised of:

at least one programmable bus masking register to store bus masking patterns;

at least one programmable breakpoint condition register to store the breakpoint condition; and

at least one programmable counter value register to store a value representing a number of breakpoint conditions to be detected before a breakpoint event results.

22. A programmable breakpoint unit comprising:

a programmable configuration logic to configure the breakpoint unit to detect a specified bus event on a selected bus;

a bus select logic to select one bus from a plurality of busses, where the bus select logic has a plurality of bus interfaces at which the plurality of busses are coupled to the breakpoint unit;

an event detection logic to detect an occurrence of a specified bus event on the selected bus by comparing data on the selected bus with the specified bus event; and

a breakpoint controller logic to take control of both busses when the event detection logic detects the specified bus event.

23. The breakpoint unit of claim 22 where the programmable configuration logic comprises:

at least one programmable control register to control the general functionality of the breakpoint unit;

at least one programmable bus masking register to store bus masking patterns;

at least one programmable breakpoint condition register to store a breakpoint condition; and

at least one programmable counter value register to store a value representing a number of breakpoint conditions that are to be detected before a breakpoint event results.

24. A programmable breakpoint unit embedded in a device and coupled to a plurality of busses comprising:

means for selecting a bus from the plurality of busses coupled to the breakpoint unit;

means for detecting a specified bus event on the selected bus,

means for breaking and taking control of the device when the occurrence of the specified bus event is detected.

25. A method of monitoring a device with multiple busses, said method comprising:

programming a configuration logic with a bus selection and a specified bus event;

selecting a bus from a plurality of busses coupled to a multi-bus breakpoint unit based on the bus selection programmed into the configuration logic;

for each bus event on the selected bus, comparing data on the selected bus with the bus event programmed into the configuration logic;

taking control of the device and the plurality of busses on occurrence of the specified bus event.