Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity

• US 6,753,205 B2
• Filed: 01/27/2003
• Issued: 06/22/2004
• Est. Priority Date: 09/13/2001
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Halahan, Patrick B.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US10/352,607
• Publication Number:
  US 20030148552A1
• Time in Patent Office: 512 Days
• Field of Search: 438/106-100, 438/118, 438/127, 438/455, 438/456, 438/459
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Semiconductor dies are bonded to contact pads formed in a substrate'"'"'s cavity. Vias through the substrate open into the cavity. Conductive lines passing through the vias connect the contact pads in the cavity to contact pads on another side of the substrate. A passage in the substrate opens into the cavity and provides an escape or pressure relief path for material filling the cavity. The passage can also be used to introduce material into the cavity.

Claims

1. A manufacturing method comprising:

forming or more vias in a first substrate of a semiconductor material having a first side and a second side opposite to the first side, wherein the vias are formed in the second side, wherein the vias do not go through the first substrate;

forming a dielectric and a conductor in at least one of the vias;

forming a mask over the first side of the first substrate to define a cavity;

removing material from the first side of the first substrate to form said cavity, wherein the material removing operation comprises;

removing semiconductor material of the first substrate to expose the dielectric on the first side of the first substrate;

after exposing the dielectric on the first side of the first substrate, removing the dielectric to expose the conductor;

wherein at a conclusion of the material removing operation, the conductor protrudes on the first side in the cavity, and wherein one or more first contact pads are made in the cavity using the protruding conductor;

bonding a contact pad of a first semiconductor die to one of the first contact pads to cause the contact pad of the first semiconductor die to adhere to the one of the first contact pads;

attaching, and electrically connecting, one or more second semiconductor dies to the second side of the first substrate.

2. The method of claim 1 wherein attaching and electrically connecting the one or more second semiconductor dies comprises electrically connecting a second contact pad on the second side of the first substrate to a third contact pad of at least one second die, the second contact pad being connected to one of the first contact pads by one or more of conductive lines that include said conductor.

3. The method of claim 2 wherein the second contact pad is either (a) bonded to the third contact pad to adhere to the third contact pad, or (b) is connected to the third contact pad by a discrete wire.

4. The method of claim 1 further comprising attaching a wiring substrate to the first substrate, the first substrate and the wiring substrate at least partially enclosing the cavity.

5. The method of claim 4 wherein the first substrate comprises a passage connecting the cavity to the first substrate'"'"'s surface other than a surface in which the cavity is formed.

6. The method of claim 4 further comprising attaching an integrated circuit to the wiring substrate and attaching the wiring substrate to the first substrate so that the integrated circuit is located in the cavity.

7. The method of claim 4 further comprising bonding a wire to a contact pad on the second side of the first semiconductor substrate and to a contact pad on the wiring substrate to connect the contact pad on the second side of the first semiconductor substrate to the contact pad on the wiring substrate.

8. A manufacturing method comprising:

forming a cavity in a first surface of a first substrate, the cavity having sidewalls, forming one or more grooves in the first surface, each groove connecting the cavity to the first substrate'"'"'s surface other than the first surface, and forming one or more first contact pads in the cavity;

placing one or more semiconductor integrated circuits into the cavity and bonding one or more contact pads of the one or more semiconductor integrated circuits to the one or more first contact pads to cause the one or more contact pads of the one or more semiconductor integrated circuits to adhere to the one or more first contact pads;

covering the cavity with a wiring substrate, and electrically connecting a contact pad on the wiring substrate to a contact pad on the first substrate, the first substrate and the wiring substrate completely enclosing the cavity except for the one or more grooves.

9. The method of claim 8 wherein each of the one or more grooves provides:

(a) a pressure-relief and/or escape path for material in the cavity, and/or (b) an inlet for injecting a material into the cavity.

10. The method of claim 8 wherein the grooves are not as deep as the cavity, the depth being a dimension perpendicular to the first surface.

11. The method of claim 8 wherein the first substrate comprises a semiconductor substrate, wherein the cavity and the grooves are formed in the semiconductor substrate, and the method further comprises:

forming one or more vias each of which passes through the semiconductor substrate, wherein each first contact pad is provided by a conductive layer formed in one of the vias and protruding out of one of the vias.

12. The method of claim 8 wherein the cavity and the one or more grooves are formed simultaneously.

13. The method of claim 8 wherein the first substrate is a semiconductor substrate.

14. The method of claim 13 wherein forming the cavity and the one or more grooves comprises a masked etch which simultaneously etches the first surface of the semiconductor substrate at the location of the cavity and at the location of the one or more grooves.

15. The method of claim 14 wherein during at least a portion of the masked etch, the one or more grooves are etched slower than the cavity, resulting in the one or more grooves being not as deep as the cavity.

16. The method of claim 15 wherein each of the one or more grooves is more narrow than the cavity.