Semiconductor device and method for fabricating the same

• US 6,753,574 B2
• Filed: 03/23/2001
• Issued: 06/22/2004
• Est. Priority Date: 10/25/2000
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Yamaguchi, Seiichiro, Amano, Isao, Kai, Mitsuaki
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Yevsikov, V.
• Application Number:
  US09/815,010
• Publication Number:
  US 20020048972A1
• Time in Patent Office: 1,187 Days
• Field of Search: 257/374, 257/371, 257/372, 257/331, 257/332, 257/341, 257/401, 257/520, 257/622, 257/330, 257/333, 438/272, 438/589, 438/527, 438/682, 438/307, 438/270, 438/283
• US Class Current: 257/331
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The semiconductor device includes: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.

Claims

1. A semiconductor device comprising:

a semiconductor layer including;

a channel region;

a source region and a drain region sandwiching the channel region; and

a body region connected to the channel region and being adjacent to the source region and the drain region;

a gate electrode formed above the channel region interposing a gate insulation film therebetween;

a dummy electrode formed above the body region near an interface between the drain region and the body region, and electrically insulated with the gate electrode; and

a body contact region formed in the body region except a region where the dummy electrode is formed.

2. A semiconductor device according to claim 1, wherein

the dummy electrode is extended above the body region near an interface between the source region and the body region.

3. A semiconductor device according to claim 1, wherein

the gate electrode and the dummy electrode are formed of the same conducting layer.

4. A semiconductor device according to claim 1, further comprising:

a silicide film formed on the semiconductor layer except a region between the gate electrode and the dummy electrode.

5. A semiconductor device according to claim 1, wherein

the gate electrode and the dummy electrode are formed of different conducting layers from each other.

6. A semiconductor device comprising:

a semiconductor layer including;

a channel region;

a source region and a drain region sandwiching the channel region; and

a body region connected to the channel region and being adjacent to the source region and the drain region;

a gate electrode formed above the channel region interposing a gate insulation film therebetween;

a dummy electrode formed above the body region near an interface between the drain region and the body region, being integral with the gate electrode, and formed in a comb-shaped; and

a body contact region formed in the body region except a region where the dummy electrode is formed.

8. A semiconductor device according to claim 6, further comprising:

a silicide film formed on the semiconductor layer except that in gaps between the comb-shaped dummy electrode.

7. A semiconductor device comprising:

a semiconductor layer including;

a channel region;

a source region and a drain region sandwiching the channel region; and

a body region connected to the channel region and being adjacent to the source region and the drain region;

a gate electrode formed above the channel region interposing a gate insulation film therebetween;

a dummy electrode formed above the body region near an interface between the drain region and the body region, being integral with the gate electrode, and formed in a pattern having an inside portion therefor cut out; and

a body contact region formed in the body region except a region where the dummy electrode is formed.

9. A semiconductor device according to claim 7, further comprising:

a silicide film formed on the semiconductor layer except that in a cut-out region of the dummy electrode.

10. A semiconductor device comprising:

a semiconductor layer including;

a channel region;

a source region and a drain region sandwiching the channel region; and

a body region connected to the channel region and being adjacent to the source region and the drain region;

a gate electrode formed above the channel region interposing a gate insulation film therebetween;

a dummy electrode formed above the body region near an interface between the drain region and the body region, and being integral with the gate electrode; and

a body contact region formed in the body region except a region where the dummy electrode is formed,

a capacitance per a unit area of a capacitor formed by the dummy electrode being smaller than a capacitance per the unit area of a capacitor formed by the gate electrode.

11. A semiconductor device comprising:

a semiconductor layer including;

a channel region;

source region and a drain region sandwiching the channel region;

a body contact region; and

a lead-out region interconnecting the channel region and the body contact region;

a device isolation film formed, surrounding the bordering edge of the semiconductor layer;

a gate electrode formed above the channel region interposing a gate insulation film therebetween; and

a first sidewall insulation film formed on a side wall of the gate electrode,

a width of the lead-out region being smaller than a sum of a width of the gate electrode and a width of the first sidewall insulation film formed on both sides of the gate electrode, and the lead-out region being insulated with the first sidewall insulation film.

12. A semiconductor device according to claim 11, wherein the source/drain regions each includes:

a first impurity diffused region formed, spaced from a vicinity of a region below the gate electrode; and

a second impurity diffused region extended from a vicinity of a region below the gate electrode, and being shallower than the first impurity diffused region,

the second impurity diffused region being spaced from the device isolation film.

13. A semiconductor device comprising:

a semiconductor layer including;

a channel region;

source/drain regions sandwiching the channel region;

a body contact region; and

a lead-out region interconnecting the channel region and the body contact region;

a device isolation film formed, surrounding the bordering edge of the semiconductor layer;

a gate electrode formed above the channel region interposing a gate insulation film therebetween;

a first sidewall insulation film formed on a side wall of the gate electrode; and

a second sidewall insulation film formed on a side wall of the device isolation film, and

covering the bordering edge of the semiconductor layer;

a width of the lead-out region being smaller than a sum of a width of the gate electrode, a width of the first sidewall insulation film formed on both side walls of the gate electrode and a width of the second sidewall insulation film formed on both side walls of the device isolation film, and the lead-out region being insulated with the first sidewall insulation film and the second sidewall insulation film.

14. A semiconductor device according to claim 13, wherein the source/drain regions each includes:

a first impurity diffused region formed, spaced from a vicinity of a region below the gate electrode; and

a second impurity diffused region extended from a vicinity of a region below the gate electrode, and being shallower than the first impurity diffused region,

the second impurity diffused region being spaced from the device isolation film.

15. A semiconductor device comprising:

a semiconductor layer including;

a first channel region;

a first source/drain region and a second source/drain region sandwiching the first channel region;

a second channel region;

a third source/drain region sandwiching the second channel region with the second source/drain region; and

a body region connected to the first channel region and the second channel region, being adjacent to the second source/drain region;

a first gate electrode formed above the first channel region interposing a first gate insulation film therebetween;

a second gate electrode formed above the second channel region interposing a second gate insulation film therebetween;

a dummy electrode formed above the body region, and electrically insulated with the first gate electrode and the second gate electrode; and

a body contact region formed in the body region except a region where the dummy electrode is formed.

16. A semiconductor device according to claim 15, wherein the dummy electrode is in common with a first transistor having the first gate electrode and a second transistor having the second gate electrode.

17. A semiconductor device comprising:

a semiconductor layer including;

a channel region;

source/drain regions sandwiching the channel region; and

a body region connected to the channel region and being adjacent to the source/drain regions;

a gate electrode formed above the channel region interposing a gate insulation film therebetween;

a dummy electrode formed above the body region, extending to a perpendicular direction of an extension of the gate electrode, having a concave surrounding the gate electrode partly, and electrically insulated from the gate electrode; and

a body contact region formed in the body region.

18. A semiconductor device according to claim 17, further comprising:

a silicide film formed on the semiconductor layer except a region between the gate electrode and the dummy electrode.