Economical high density chip carrier

• US 6,753,612 B2
• Filed: 04/05/2001
• Issued: 06/22/2004
• Est. Priority Date: 04/05/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Youngs, Thurston B. Jr., Adae-Amoakoh, Sylvia, Markovich, Voya R., Kresge, John S.
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Andujar, Leonardo
• Application Number:
  US09/827,014
• Publication Number:
  US 20020145203A1
• Time in Patent Office: 1,174 Days
• Field of Search: 257/690, 257/691, 257/773, 257/778, 257/774, 257/758, 174/256, 174/266
• US Class Current: 257/774
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/0305 Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
• CPC Class Codes: H05K 2201/035 Paste overlayer, i.e. conductive paste or solder paste over conductive layer
• CPC Class Codes: H05K 3/061 Etching masks
• CPC Class Codes: H05K 3/062 consisting of metals or alloys or metallic inorganic compounds H05K3/065 takes precedence
• CPC Class Codes: H05K 3/247 Finish coating of conductors by using conductive pastes, inks or powders
• CPC Class Codes: H05K 3/3485 Applying solder paste, slurry or powder thick film methods for applying conductive paste or ink patterns H05K3/12
• CPC Class Codes: H05K 3/4038 Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: H05K 3/4069 for via connections in organic insulating substrates
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4652 : Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence

Abstract

A flip-chip joinable substrate having non-plated-on contact pads. The substrate has an external metal foil layer upon a dielectric layer upon a patterned internal metal layer having an internal contact area. An area of the external metal foil layer above the internal contact area is selected. A microvia cavity extending to the internal contact area is perforated centrally within the selected area and is filled with a mass of conductive paste forming an external contact pad. The external contact pad is used as an etch mask for removing the adjacent external metal foil.

Claims

1. An electronic structure comprising:

a substrate having a dielectric layer between a first metal layer and a second metal layer, the second metal layer being disposed above the first metal layer, the first metal layer having a first contact area, the second metal layer having a top surface that includes a selected area disposed above the first contact area;

a microvia cavity within the selected area being disposed through the second metal layer and through the dielectric layer and extending to the first contact area of the first metal layer; and

a mass of a single conductive material, wherein a first portion of the mass forms an external layer upon the selected area of the top surface of the second metal layer such that the external layer is external to the microvia cavity and external to the substrate, and wherein a second portion of the mass totally fills the microvia cavity and is in contact with the first contact area of the first metal layer.

2. The structure of claim 1, wherein the mass of the single conductive material conformally fills the microvia cavity.

3. The structure of claim 1, wherein the mass of the single conductive material has a planar surface forming a contact pad located parallel to and opposite the first contact area of the first metal layer.

4. The structure of claim 1, wherein selected area is approximately centered around the first contact area.

5. The structure of claim 4, wherein the second metal layer within the selected area is approximately centered around the microvia cavity.

6. The structure of claim 1, wherein the second metal layer within the selected area is approximately centered around the first contact area.

7. The structure of claim 1, wherein the second metal layer contains a flat copper ring around the microvia cavity.

8. The structure of claim 1, wherein the microvia cavity includes a truncated cone-shaped hole in the dielectric layer.

9. The structure of claim 1, wherein the mass of the single conductive material comprises at least one of a solder paste, a reflowable solder, a conductive paste, and a conductive adhesive.

10. The structure of claim 1, wherein the selected area is a planar area.

11. The structure of claim 1, wherein the selected area is a planar area that is about parallel to a planar top surface of the first metal layer.

12. The structure of claim 1, wherein an etch rate of the single conductive material is less than an etch rate of a metal comprised by the second metal layer.

13. The structure of claim 1, wherein the single conductive material is bondable to a wall of the microvia cavity.

14. An assembly comprising:

a semiconductor chip;

a substrate having a dielectric layer between a first metal layer and a second metal layer, the second metal layer being disposed above the first metal layer, the first metal layer having a first contact area, the second metal layer having a top surface that includes a selected area disposed above the first contact area;

a microvia cavity within the selected area being disposed through the second metal layer and through the dielectric layer and extending to the first contact area of the first metal layer; and

a continuous mass of a single conductive material, wherein a first portion of the mass forms an external layer upon the selected area of the top surface of the second metal layer such that the external layer is external to the microvia cavity and external to the substrate, wherein a second portion of the mass totally fills the microvia cavity and is in contact with the first contact area of the first metal layer, and wherein the semiconductor chip is electrically connected to the mass of the single conductive material.

15. The assembly of claim 14, wherein the selected area is a planar area.

16. The assembly of claim 14, wherein the selected area is a planar area that is about parallel to a planar top surface of the first metal layer.

17. The assembly of claim 14, wherein an etch rate of the single conductive material is less than an etch rate of a metal comprised by the second metal layer.

18. The assembly of claim 14, wherein the single conductive material is bondable to a wall of the microvia cavity.

19. An assembly comprising:

a semiconductor chip;

a substrate having a dielectric layer between a first metal layer and a second metal layer, the second metal layer being disposed above the first metal layer, the first metal layer having a first contact area, the second metal layer having a top surface that includes a selected area disposed above the first contact area;

a microvia cavity within the selected area being disposed through the second metal layer and through the dielectric layer and extending to the first contact area of the first metal layer; and

a mass of a single conductive material forming a layer upon the selected area of the top surface of the second metal layer and totally filling the microvia cavity and being in contact with the first contact area of the first metal layer, wherein the semiconductor chip is electrically connected to the mass of the single conductive material, wherein the single conductive material is not bondable to a wall of the microvia cavity.

20. An electronic structure comprising:

a substrate having a dielectric layer between a first metal layer and a second metal layer, the second metal layer being disposed above the first metal layer, the first metal layer having a first contact area, the second metal layer having a top surface that includes a selected area disposed above the first contact area;

a microvia cavity within the selected area being disposed through the second metal layer and through the dielectric layer and extending to the first contact area of the first metal layer; and

a mass of a single conductive material forming a layer upon the selected area of the top surface of the second metal layer and totally filling the microvia cavity and being in contact with the first contact area of the first metal layer, wherein the single conductive material is not bondable to a wall of the microvia cavity.