Single event upset immune logic family

• US 6,753,694 B2
• Filed: 12/16/2002
• Issued: 06/22/2004
• Est. Priority Date: 09/29/2000
• Status: Active Grant

• Current Assignee: Johns Hopkins University
• Original Assignee: Johns Hopkins University
• Inventors: Eaton, Harry A.
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/320,137
• Publication Number:
  US 20030122571A1
• Time in Patent Office: 554 Days
• Field of Search: 326/9, 326/10, 326/13, 326/112, 326/119, 326/121
• US Class Current: 326/13
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/00392 by circuit redundancy H03K19/0075 takes precedence

Abstract

A collection of logic gates that provide single event upset (SEU) immunity. The family of gates include an inverter, a two-input NOR gate, a two-input NAND gate, a three-input AND-NOR gate, and a three-input OR-NAND as well as a static RAM bit cell. SEU immunity is obtained by constructing each logic element with a redundant set of inputs and using two copies of each such logic element to provide redundant outputs. The design of a logic element is such that when the redundant inputs agree (i.e., each has the same logic value), then the output of the logic element implements the logic function. However, when any pair of redundant inputs disagree, then the output of the logic element is disconnected (tri-state), which preserves the previous output value. SEU events only affect one of the logic elements in the pair, and this upset can not propagate through other logic elements because of the tri-state function.

Claims

1. A single event upset (SEU) immune three-input AND-NOR circuit comprising:

primary p-channel CMOS transistors, T1, T3 and T5, and redundant p-channel CMOS transistors, T2, T4 and T6; and

primary n-channel CMOS transistors, T8, T10 and T12, and redundant n-channel CMOS transistors, T7, T9 and T11;

wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that,

a first primary input, A1, is coupled with the gate of T1 and the gate of T12;

a first redundant input, A2, is coupled with the gate of T2 and the gate of T11;

a second primary input, B1, is coupled with the gate of T3 and the gate of T10;

a second redundant input, B2, is coupled with the gate of T4 and the gate of T9;

a third primary input, C1, is coupled with the gate of T5 and the gate of T8;

a third redundant input, C2, is coupled with the gate of T6 and the gate of T7;

the source of T1 is coupled with a power supply;

the drain of T1 is coupled with the source of T2;

the drain of T2 is coupled with the drain of T4;

the source of T3 is coupled with the power supply;

the drain of T3 is coupled with the source of T4;

the drain of T4 is coupled with the drain of T2;

the source of T5 is coupled with the drain of T2 and the drain of T4;

the drain of T5 is coupled with the source of T6;

the drain of T6 is coupled with an output, Y;

the drain of T7 is coupled with the output, Y;

the source of T7 is coupled with the drain of T8;

the source of T8 is coupled with ground;

the drain of T9 is coupled with the output, Y;

the source of T9 is coupled with the drain of T10;

the source of T10 is coupled with the drain of T11;

the source of T11 is coupled with the drain of T12; and

the source of T12 is coupled with ground.

2. A single event upset (SEU) immune three-input OR-NAND circuit comprising:

primary p-channel CMOS transistors, T1, T3 and T5, and redundant p-channel CMOS transistors, T2, T4 and T6; and

primary n-channel CMOS transistors, T8, T10 and T12, and redundant n-channel CMOS transistors, T7, T9 and T11;

wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that,

a first primary input, A1, is coupled with the gate of T1 and the gate of T12;

a first redundant input, A2, is coupled with the gate of T2 and the gate of T11;

a second primary input, B1, is coupled with the gate of T3 and the gate of T10;

a second redundant input, B2, is coupled with the gate of T4 and the gate of T9;

a third primary input, C1, is coupled with the gate of T5 and the gate of T8;

a third redundant input, C2, is coupled with the gate of T6 and the gate of T7;

the source of T1 is coupled with a power supply;

the drain of T1 is coupled with the source of T2;

the drain of T2 is coupled with the source of T3;

the drain of T3 is coupled with the source of T4;

the drain of T4 is coupled with an output, Y;

the source of T5 is coupled with the power supply;

the drain of T5 is coupled with the source of T6;

the drain of T6 is coupled with the output, Y;

the drain of T7 is coupled with the output, Y;

the source of T7 is coupled with the drain of T8;

the source of T8 is coupled with drain of T11;

the drain of T9 is coupled with the drain of T11;

the source of T9 is coupled with the drain of T10;

the source of T10 is coupled with ground;

the drain of T11 is coupled with the source of T8 and the drain of T9; and

the source of T11 is coupled with drain of T12; and

the source of T12 is coupled with ground.