Multi-mode amplifier bias circuit

• US 6,753,734 B2
• Filed: 02/04/2003
• Issued: 06/22/2004
• Est. Priority Date: 06/06/2001
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Anadigics Incorporated (Coherent Corp.)
• Inventors: Liwinski, Henry Z., Arell, Thomas W.
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US10/358,371
• Publication Number:
  US 20030146790A1
• Time in Patent Office: 504 Days
• Field of Search: 330/296, 330/51, 330/288, 330/261, 330/291
• US Class Current: 330/296
• CPC Class Codes: G05F 3/265 using bipolar transistors only
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 3/343 with semiconductor devices only

Abstract

There is disclosed a bias circuit exhibiting good stability over variations in temperature and power supply voltage and capable of generating a plurality of discrete levels of output current for biasing RF power amplifier. In accordance with the invention, the bias circuit includes (1) a master transistor connected to the slave transistor in a current-mirror configuration and having two parallel-connected transistor elements, (2) a switch connected to at least one transistor element to control its operation, and (3) a feedback circuit by which the voltage at the collector of the master transistor may be fed back to control the voltages at the bases of the master transistor and the slave transistor. Moreover, the bias circuit can be operated from a power supply voltage that is just above twice the value of the base-emitter voltage of the transistor in the circuit.

Claims

1. A circuit for biasing an RF amplifying transistor, the circuit comprising:

A. a composite master transistor connected to the RF amplifying transistor in a current-mirror configuration, the composite master transistor comprising at least two transistor elements;

B. a buffering transistor having a control terminal connected to a current-sink terminal of the master transistor and providing an output connected to control terminals of the composite master transistor and the RF amplifying transistor and the current-sink terminal of the RF amplifying transistor; and

C. a switch connected to at least one of the at least two transistor elements, wherein in a first state, the switch disables one of the at least two transistor elements, thereby rendering the composite master transistor suitable to bias the RF amplifying transistor at a first operating point, and in a second state, the switch enables one of said at least two transistor elements, thereby rendering the master transistor suitable to bias the RF amplifying transistor at a second operating point.

2. The circuit of claim 1, wherein the slave transistor is a composite transistor comprising at least two transistor elements.

3. The circuit of claim 2, wherein the switch is connected to at least one of the at least two transistor elements of the composite slave transistor.

4. The circuit of claim 1 further comprising at least one resistors connected between the control terminal of the at least one of the at least two transistor elements and a current-source terminal of the buffering transistor.

5. The circuit of claim 1, further comprising at least one resistor connected between the current-sink terminal of the at least one of the at least two transistor elements and the control terminal of the buffering transistor.

6. The circuit of claim 1, wherein the switch comprises a transistor switch.

7. The circuit of claim 6, wherein the switch is coupled to the control terminal of the at least one of the at least two transistor elements.

8. The circuit of claim 6, wherein the switch is coupled to the current-sink terminal of one of the at least two transistor elements.

9. The circuit of claim 1, wherein the switch comprises a push-pull emitter-follower coupled to the control terminal of one of the at least two transistor elements.

10. The circuit of claim 1, wherein the switch operates automatically in response to a control signal.

11. The circuit of claim 1, wherein the switch operates in response to a change in a one of a modulation scheme and a drive level of an input RF signal.

12. The circuit of claim 1, wherein all transistor elements have equal areas.

13. The circuit of claim 1, wherein all transistor elements have different areas.

14. The circuit of claim 1, wherein all transistor elements are matched.

15. The circuit of claim 1, wherein the master transistor has the equal size area to the RF amplifying transistor'"'"'s area.

16. The circuit of claim 1, wherein the composite master transistor has a different size area from the RF amplifying transistor.

17. The circuit of claim 1, wherein the area of the master transistor is a multiple of the area of the RF amplifying transistor.

18. The circuit of claim 1, wherein the master transistor is matched to the RF amplifying transistor.

19. The circuit of claim 1 further comprising a non-inverting amplifier connected between the current-sink terminal of the composite master transistor and the control terminal of the buffering transistor.

20. The circuit of claim 19, wherein the non-inverting amplifier comprises two cascaded transistors.

21. The circuit of claim 20, wherein the circuit can operate from a power supply that produces a voltage that is about twice base-emitter voltage of the RF amplifying transistor.

22. The circuit of claim 1, wherein all the transistors are implemented as one of BJTs, FETs, MESFETs, MOSFETs, HFETs, HBTs, HEMTs, and PHEMTs.

23. A current mirror amplifier (CMA) comprises:

A. a composite master transistor, the composite master transistor comprising at least two transistor elements;

B. a composite slave transistor, the composite slave transistor comprising at least two transistor elements;

C. a buffering transistor having a control terminal connected to a current-sink terminal of the master transistor and providing an output connected to control terminals of the composite master transistor and the composite slave transistor and the current-sink terminal of the composite slave transistor;

D. a first switch connected to at least one of the at least two transistor elements of the composite master transistor; and

E. a second switch connected to at least one of the at least two transistor elements of the composite slave transistor.

24. The CMA of claim 23, wherein the slave transistor is a RF amplifying transistor.

25. The CMA of claim 23 further comprising at least one resistors connected between the control terminal of the at least one of the at least two transistor elements and a current-source terminal of the buffering transistor.

26. The CMA of claim 23, wherein the first switch and the second switch operate automatically in response to a control signal.

27. The CMA of claim 23, wherein the first switch and the second switch operate in response to a change in a one of a modulation scheme and a drive level of an input RF signal.

28. The CMA of claim 23, wherein all transistor elements have equal areas.

29. The CMA of claim 23, wherein all transistor elements have different areas.

30. The CMA of claim 23, wherein all transistor elements are matched.

31. The CMA of claim 23, wherein the master transistor has the equal size area to the RF amplifying transistor'"'"'s area.

32. The CMA of claim 23, wherein the master transistor has a different size area from the RF amplifying transistor.

33. The CMA of claim 23, wherein the area of the master transistor is a multiple of the area of the RF amplifying transistor.

34. The CMA of claim 23, wherein the master transistor is matched to the RF amplifying transistor.

35. The CMA of claim 23 further comprising a non-inverting amplifier connected between the current-source terminal of the composite master transistor and the control terminal of the buffering transistor.

36. The CMA of claim 35, wherein the non-inverting amplifier comprises two cascaded transistors.

37. The CMA of claim 36, wherein the circuit can operate from a power supply that produces a voltage that is about twice base-emitter voltage of the RF amplifying transistor.

38. The CMA of claim 23, wherein the transistors in the circuit are implemented as one of BJTs, FETs, MESFETs, MOSFETs, HFETs, HBTs, HEMTs, and PHEMTs.

39. A method of biasing an RF amplifying transistor having at least two operating points via a bias circuit comprising a composite master transistor connected to the RF amplifying transistor in a current-mirror configuration and comprising at least two transistor elements, the method comprising the steps of:

A. providing a path for a reference current through a current-sink terminal of the composite master transistor; and

B. providing one of the at least two transistor elements to generate a first bias signal; and

C. providing another of the at least two transistor elements to generate a second bias signal, wherein second bias signal is different from the first bias signal.

40. The method of claim 39, wherein the first bias signal is a fraction of the reference current.

41. The method of claim 39, wherein the second bias signal is a fraction of the reference current.

42. The method of claim 39 further comprising the step of applying an RF signal to the base of the RF amplifying transistor.

43. A method for manufacturing a bias circuit comprising the steps of:

A. fabricating a composite transistor having at least two parallel-connected transistor elements;

B. fabricating a buffering transistor, the buffering transistor being connected as emitter-follower between the current-source and control terminals of the composite transistor; and

C. connecting a switch to at least one of the at least two transistor elements.

44. The method of claim 43 further comprising the step of fabricating at least two resistors respectively connected to the control terminals of the at least two transistor elements.

45. The method of claim 43 further comprising the step of fabricating at least two resistors respectively connected to the current-source terminals of the at least two transistor elements.

46. The method of claim 43, wherein the composite transistor, the buffering transistor and the switch are fabricated on a monolithic circuit.

47. The method of claim 43, wherein the composite transistor, the buffering transistor and the switch are fabricated on a hybrid circuit.