Impedance tuning circuit

• US 6,753,738 B1
• Filed: 06/25/2002
• Issued: 06/22/2004
• Est. Priority Date: 06/25/2001
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Baird, Rex T.
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): TRA, ANH QUAN
• Application Number:
  US10/180,783
• Time in Patent Office: 728 Days
• Field of Search: 331/56, 331/167, 331/177.R, 331/179, 331/117.R, 331/117.FE, 331/177.Y, 331/46, 331/25, 331/16
• US Class Current: 331/25
• CPC Class Codes: H03B 5/1206 using multiple transistors for amplification
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/124 the means comprising a voltage dependent capacitance
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 7/0332 with an integrator-detector

Abstract

A feedback system such as a phase locked loop (PLL) includes a second feedback loop which responds when a VCO control voltage is near either end of its range, by slowly adjusting additional tuning elements which control the VCO frequency. The second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first traditional feedback loop adjusts the control voltage quickly enough in a direction toward its mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop advantageously incorporates one or more digital control signals which preferably change no more than one bit at a time and with a controlled slow ramp rate. As a result, the PLL maintains phase accuracy so that the operation of the PLL, including subtle specifications such as input data jitter tolerance or output jitter generation when used for clock and data recovery applications, is not negatively impacted. An impedance tuning feedback system provides a resistance between two nodes which is proportional to a reference resistance, and preferably incorporates slow digital switching to result in near perturbation-free state changes over the tuning range of the resistance.

Claims

1. A controlled resistance circuit forming a resistance between a first node and a second node having a controlled magnitude proportional to a reference resistance, said circuit comprising:

a first variable resistance circuit connected between the first node and the second node, said first variable resistance circuit having an analog portion responsive to an analog control signal and having a digital portion responsive to a digital control signal, and whose magnitude is responsive to both the analog control signal and the digital control signal;

a second variable resistance circuit connected between a third node and a fourth node, said second variable resistance circuit having an analog portion responsive to the analog control signal and having a digital portion responsive to the digital control signal, and whose magnitude, for a given value of the analog control signal and a given value of the digital control signal, is proportional to the magnitude of the first variable resistance circuit;

a first feedback circuit responsive to a voltage developed across the second variable resistance circuit by a controlled first current flowing therethrough, for generating the analog control signal accordingly to adjust the magnitude of the second variable resistance circuit toward a magnitude which is proportional to the reference resistance;

a second feedback circuit responsive to the analog control signal when the analog control signal is driven outside a predetermined range, for generating the digital control signal to accordingly further adjust the magnitude of the second variable resistance circuit in like direction as that resultant from the analog control signal being driven outside the predetermined range, so that the first feedback circuit drives the analog control signal back within the predetermined range;

said first and second feedback circuits being arranged to generally maintain the analog control signal within the predetermined range and to adjust the magnitude of the second variable resistance circuit to a magnitude proportional to the reference resistance, thereby likewise adjusting the magnitude of the first variable resistance circuit to a controlled magnitude which is proportional to the reference resistance.

2. The invention as recited in claim 1 wherein the second feedback circuit is configured to affect the magnitude of the first and second variable resistance circuits substantially more slowly than does the first feedback circuit, so that the first and second feedback circuits together control the magnitude of the first and second variable resistance circuits without significant perturbation.

3. The invention as recited in claim 1 wherein the first, second, third, and fourth nodes are all different nodes.

4. The invention as recited in claim 1 wherein the second and fourth nodes are coupled to a signal reference node.

5. The invention as recited in claim 1 wherein the reference resistance comprises a resistor external to an integrated circuit upon which the controlled resistance circuit is implemented.

6. The invention as recited in claim 1 wherein the reference resistance comprises a resistor integral to an integrated circuit upon which the controlled resistance circuit is implemented.

7. The invention as recited in claim 6 wherein the integral reference resistance is trimmable during manufacture or testing of the integrated circuit upon which the controlled resistance circuit is implemented.

8. The invention as recited in claim 1 further comprising:

a third variable resistance circuit connected between a fifth node and a sixth node, said third variable resistance circuit having an analog portion responsive to the analog control signal and having a digital portion responsive to the digital control signal, and whose magnitude, for a given value of the analog control signal and a given value of the digital control signal, is proportional to the magnitude of the second variable resistance circuit, for providing a controlled resistance between the fifth and sixth nodes which is proportional to the reference resistance.

9. The invention as recited in claim 8 wherein the first, second, third, fourth, fifth, and sixth nodes are all different nodes.

10. The invention as recited in claim 8 wherein the second, fourth, and sixth nodes are coupled to a signal reference node.

11. The invention as recited in claim 1 wherein:

the digital control signal comprises a plurality M of digital switch control signals forming a multiple-bit digital word;

the digital portion of the first variable resistance circuit comprises a plurality M of individual resistance circuits, each having a respective weight and each responsive to a corresponding one of the plurality M of digital switch control signals, and each having a first terminal coupled to the first node and a second terminal coupled to the second node; and

the digital portion of the second variable resistance circuit comprises a plurality M of individual resistance circuits, each having a respective weight and each responsive to a corresponding one of the plurality M of digital switch control signals, and each having a first terminal coupled to the third node and a second terminal coupled to the fourth node.

12. The invention as recited in claim 11 wherein the respective weight of each of the plurality M of individual resistance circuits are substantially equal.

13. The invention as recited in claim 11 wherein the respective weight of each of the plurality M of individual resistance circuits are not all substantially equal.

14. The invention as recited in claim 11 wherein the respective weight of each of the plurality M of individual resistance circuits are binary weighted.

15. The invention as recited in claim 11 wherein:

the second feedback circuit is configured to cause no more than one of the plurality of digital switch control signals to transition at a given time.

16. The invention as recited in claim 11 wherein:

the second feedback circuit is configured to cause, at times, more than one of the plurality of digital switch control signals to simultaneously transition.

17. The invention as recited in claim 11 wherein:

the second feedback circuit is configured so that each of the plurality of digital switch control signals transitions between a first quiescent level and a second quiescent level with a controlled slow transition time.

18. The invention as recited in claim 11 wherein:

the second feedback circuit is configured to cause no more than one of the plurality of digital switch control signals to transition at a given time, and to cause each of the plurality of digital switch control signals to transition between a first quiescent level and a second quiescent level with a controlled slow transition time.

19. The invention as recited in claim 11 wherein:

each individual resistance circuit includes a switch circuit having a switch control terminal coupled to receive a corresponding one of the plurality of digital switch control signals.

20. The invention as recited in claim 19 wherein:

each individual resistance circuit further comprises at least one resistor circuit coupled between one of the respective terminals of the individual resistance circuit and the respective switch circuit.

21. The invention as recited in claim 19 wherein each individual resistance circuit further comprises:

a first resistor circuit coupled between one of the respective terminals of the individual resistance circuit and the respective switch circuit; and

a second resistor circuit coupled between the other of the respective terminals of the individual resistance circuit and the respective switch circuit.

22. The invention as recited in claim 3 wherein:

the first and second nodes comprise a differential input for an integrated circuit; and

the first variable resistance circuit comprises an internal termination resistance for the differential input.

23. The invention as recited in claim 4 wherein:

the first node comprise a single-ended input for an integrated circuit; and

the first variable resistance circuit comprises an internal termination resistance for the single-ended input.

24. The invention as recited in claim 1:

wherein the first variable resistance circuit includes a first voltage divider circuit connected between the first and second nodes to generate a first common mode voltage on an intermediate node therebetween;

wherein the second variable resistance circuit includes a second voltage divider circuit connected between the third and fourth nodes to generate a second common mode voltage on an intermediate node therebetween; and

further comprising an amplifier circuit responsive to the first and second common mode voltages for driving the fourth node to a voltage which results in the second common mode voltage being substantially equal in magnitude to the first common mode voltage.

25. The invention as recited in claim 11 wherein second feedback circuit comprises:

comparison circuitry for generating at least one out-of-range (OOR) signal when the analog control signal is driven outside its predetermined range;

a digital control circuit responsive to the at least one OOR signal for increasing or decreasing the number of digital switch control signals which are driven to an active level.

26. The invention as recited in claim 25 wherein the comparison circuitry is configured to generate a first out-of-range (OOR) signal when the analog control signal is driven in a first direction outside its predetermined range and for generating a second out-of-range signal when the analog control signal is driven in a second direction opposite the first direction outside its predetermined range.

27. The invention as recited in claim 25 wherein the digital control circuit is arranged to transition each of the plurality of digital switch control signals between a first quiescent level and a second quiescent level with a controlled slow transition time.

28. The invention as recited in claim 27 wherein the digital control circuit comprises:

starved driver stages configured to drive the plurality of digital switch control signals between a first quiescent level and a second quiescent level with a deliberately degraded transition time relative to a normally sized driver stage.

29. The invention as recited in claim 27 wherein the digital control circuit comprises:

at least one slow transition generator having an output signal sharable among more than one of the plurality of digital switch control signals to drive at least a corresponding one of the plurality of digital switch control signals between a first quiescent level and a second quiescent level with a controlled slow transition time.

30. The invention as recited in claim 29 wherein the at least one slow transition generator comprises:

a digital to analog converter (DAC) responsive to a multi-bit digital control word that is sequenced through a plurality of digital values to generate a slowly decreasing or increasing value on an output thereof.

31. The invention as recited in claim 1 wherein the first feedback circuit comprises:

a second resistor circuit having a particular magnitude and coupled between the fourth node and a seventh node;

a current source circuit for generating a voltage across the second resistor circuit;

an amplifier circuit responsive to a voltage differential between the fourth and seventh nodes, for generating the analog control signal in accordance therewith.

32. The invention as recited in claim 11 wherein the analog portion of the second variable resistance circuit comprises:

at least one individual variable resistance circuit, each responsive to the analog control signal, each having a first terminal coupled to the third node and a second terminal coupled to the fourth node.

33. A computer readable medium encoding a circuit for providing a resistance between a first node and a second node having a controlled magnitude proportional to a reference resistance, said encoded circuit comprising:

a first variable resistance circuit connected between the first node and the second node, said first variable resistance circuit having an analog portion responsive to an analog control signal and having a digital portion responsive to a digital control signal, and whose magnitude is responsive to both the analog control signal and the digital control signal;

a second variable resistance circuit connected between a third node and a fourth node, said second variable resistance circuit having an analog portion responsive to the analog control signal and having a digital portion responsive to the digital control signal, and whose magnitude, for a given value of the analog control signal and a given value of the digital control signal, is proportional to the magnitude of the first variable resistance circuit;

a first feedback circuit responsive to a voltage developed across the second variable resistance circuit by a controlled first current flowing therethrough, for generating the analog control signal accordingly to adjust the magnitude of the second variable resistance circuit toward a magnitude which is proportional to the reference resistance;

a second feedback circuit responsive to the analog control signal when the analog control signal is driven outside a predetermined range, for generating the digital control signal to accordingly further adjust the magnitude of the second variable resistance circuit in like direction as that resultant from the analog control signal being driven outside the predetermined range, so that the first feedback circuit drives the analog control signal back within the predetermined range;

said first and second feedback circuits being arranged to generally maintain the analog control signal within the predetermined range and to adjust the magnitude of the second variable resistance circuit to a magnitude proportional to the reference resistance, thereby likewise adjusting the magnitude of the first variable resistance circuit to a controlled magnitude which is proportional to the reference resistance.

34. The invention as recited in claim 33 wherein:

the digital control signal comprises a plurality M of digital switch control signals forming a multiple-bit digital word;

the digital portion of the first variable resistance circuit comprises a plurality M of individual resistance circuits, each having a respective weight and each responsive to a corresponding one of the plurality M of digital switch control signals, and each having a first terminal coupled to the first node and a second terminal coupled to the second node; and

the digital portion of the second variable resistance circuit comprises a plurality M of individual resistance circuits, each having a respective weight and each responsive to a corresponding one of the plurality M of digital switch control signals, and each having a first terminal coupled to the third node and a second terminal coupled to the fourth node.

35. The invention as recited in claim 34 wherein the second feedback circuit is configured to cause no more than one of the plurality of digital switch control signals to transition at a given time, and to cause each of the plurality of digital switch control signals to transition between a first quiescent level and a second quiescent level with a deliberately slowed transition time.

36. The invention as recited in claim 33 wherein:

the first and second nodes comprise a differential input; and

the first variable resistance circuit comprises a termination resistance for the differential input.

37. A resistance circuit providing a resistance between a first node and a second node having a controlled magnitude proportional to a reference resistance, said circuit comprising:

a first variable resistance circuit connected between the first node and the second node, said first variable resistance circuit having a magnitude that is responsive to at least one control signal;

a second variable resistance circuit connected between a third node and a fourth node, said second variable resistance circuit having a magnitude that is responsive to the at least one control signal and which magnitude, for a given value of the at least one control signal, is proportional to the magnitude of the first variable resistance circuit;

a bias circuit including a first bias resistance, said bias circuit for generating a controlled reference current and a controlled bias current, wherein a ratio of the controlled bias current to the controlled reference current is proportional to the ratio of the reference resistance to the first bias resistance;

a second bias resistance having a magnitude which is proportional to that of the first bias resistance and which is implemented to track variations in the first bias resistance;

a feedback circuit arranged to compare a first voltage developed across the second bias resistance by the controlled bias current flowing therethrough against a second voltage developed across the second variable resistance circuit by the controlled reference current flowing therethrough, and to generate accordingly the at least one control signal to adjust the value of the second variable resistance circuit so that the first voltage substantially equals the second voltage, thereby resulting in the second variable resistance circuit having a magnitude proportional to the reference resistance;

whereby the first variable resistance circuit, being also responsive to the at least one control signal, likewise achieves a magnitude proportional to the reference resistance.

38. The invention as recited in claim 37 wherein the first, second, third, and fourth nodes are all different nodes.

39. The invention as recited in claim 37 wherein the second and fourth nodes are coupled to a signal reference node.

40. The invention as recited in claim 37 wherein:

the reference resistance comprises a resistor external to an integrated circuit upon which the controlled resistance circuit is implemented;

the first bias resistance is implemented having a nominal value proportional to the nominal value of the external reference resistor; and

the second bias resistance is implemented having a nominal value proportional to a desired value of the second variable resistance circuit.

41. The invention as recited in claim 37 further comprising:

a third variable resistance circuit connected between a fifth node and a sixth node different from the first, second, third, and fourth nodes, said third variable resistance circuit having a magnitude that is responsive to the at least one control signal and which magnitude, for a given value of the at least one control signal, is proportional to the magnitude of the second variable resistance circuit, for providing a controlled resistance between the fifth and sixth nodes which is proportional to the reference resistance.

42. The invention as recited in claim 37 wherein the second variable resistance circuit comprises:

at least one individual variable resistance circuit responsive to an analog control signal, having a first terminal coupled to the third node and a second terminal coupled to the fourth node; and

a plurality of individual variable resistance circuits, each responsive to a corresponding one of a plurality of digital control signals, and each having a first terminal coupled to the third node and a second terminal coupled to the fourth node.

43. The invention as recited in claim 42 wherein the feedback circuit comprises:

a control circuit for generating each of the plurality of digital control signals and configured to cause no more than one of the plurality of digital control signals to transition at a given time, and further configured to cause each of the plurality of digital control signals to transition between a first quiescent level and a second quiescent level with a deliberately slowed transition time.

44. The invention as recited in claim 42 wherein each individual variable resistance circuit comprises:

a switch circuit having a switch control terminal coupled to receive a corresponding one of the analog or digital control signals;

a first resistor circuit coupled between one of the respective terminals of the individual variable resistance circuit and the respective switch circuit; and

a second resistor circuit coupled between the other of the respective terminals of the individual variable resistance circuit and the respective switch circuit.

45. The invention as recited in claim 37 wherein:

the first variable resistance circuit comprises an internal termination resistance for the differential input signal.

46. The invention as recited in claim 37:

wherein the first variable resistance circuit includes a first voltage divider circuit connected between the first and second nodes to generate a first common mode voltage on an intermediate node therebetween;

wherein the second variable resistance circuit includes a second voltage divider circuit connected between the third and fourth nodes to generate a second common mode voltage on an intermediate node therebetween; and

further comprising an amplifier circuit responsive to the first and second common mode voltages for driving the fourth node to a voltage which results in the second common mode voltage being substantially equal in magnitude to the first common mode voltage.

47. The invention as recited in claim 42 wherein the feedback circuit comprises:

comparison circuitry for generating a first out-of-range (OOR) signal when the analog control signal is driven in a first direction outside its predetermined range and for generating a second out-of-range signal when the analog control signal is driven in a second direction opposite the first direction outside its predetermined range;

a digital control circuit responsive to the first and second OOR signals for increasing or decreasing the number of digital control signals which are driven to an active level.

48. The invention as recited in claim 43 wherein the control circuit comprises:

starved driver stages configured to drive the plurality of digital control signals between a first quiescent level and a second quiescent level with a deliberately slowed transition time.

49. The invention as recited in claim 43 wherein the control circuit comprises:

at least one slow transition generator having an output signal shared among more than one of the plurality of digital control signals to drive a corresponding one of the plurality of digital control signals between a first quiescent level and a second quiescent level with a deliberately slowed transition time.

50. The invention as recited in claim 49 wherein the at least one slow transition generator comprises:

a digital to analog converter (DAC) responsive to a multi-bit digital control word that is sequenced through a plurality of digital values to generate a slowly decreasing or increasing value on an output thereof.

51. A computer readable medium encoding a circuit, said encoded circuit as defined in claim 37.