Refresh techniques for memory data retention

• US 6,754,101 B2
• Filed: 04/25/2003
• Issued: 06/22/2004
• Est. Priority Date: 05/21/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Afghahi, Morteza Cyrus, Terzioglu, Esin, Winograd, Gil I.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/423,350
• Publication Number:
  US 20030218911A1
• Time in Patent Office: 424 Days
• Field of Search: 365/201, 365/203, 365/205, 365/207, 365/222, 365/185.21, 365/185.25, 365/185.29
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer

Abstract

A digital memory system (30) includes a memory cell (52), a bit line (50) and a charge integrity estimating module 35. The module is operative during a first mode of operation to detect whether a quantity of the charge stored in the memory cell lies within the first range of values or the second range of values, is operative during a second mode of operation to detect whether the quantity of the charge lies within a third range of values comprising a subset of the first range of values and is operative during a third mode of operation to detect whether the quantity of the charge lies within a fourth range of values comprising a subset of the second range of values.

Claims

1. In a digital memory system including a memory cell arranged to store charge corresponding to first logical value when the quantity of stored charge lies within a first range of values and corresponding to a second logical value when the quantity of stored change lies within a second range of values, apparatus testing the integrity of the data represented by the charge comprising:

a bit line with a voltage responsive to charge stored in the cell; and

a charge integrity estimating module operative during a first mode of operation to detect whether the quantity of the charge lies within the first range of values or the second range of values, operative during a second mode of operation to detect whether the quantity of the charge lies within a third range of values comprising a subset of the first range of values and operative during a third mode of operation to detect whether the quantity of the charge lies within a fourth range of values comprising a subset of the second range of values.

2. The apparatus of claim 1 wherein the second mode of operation is entered only if the quantity of charge lies within the first range of values and wherein the third mode of operation is entered only if the quantity of the charge lies within the second range of values.

3. The apparatus of claim 1 wherein the charge integrity estimating module comprises:

a reference voltage generator arranged to generate a reference voltage;

a sense amplifier arranged to generate a sense output voltage in response to the charge conducted by the bit line and the reference voltage;

a first load operative during the second mode of operation to place a first load on the sense amplifier; and

a second load operative during the third mode of operation to place a second load on the sense amplifier.

4. The apparatus of claim 3 wherein the reference voltage generator is arranged to precharge the bit line to generate a bit line precharge voltage and arranged to generate the reference voltage in response to the bit line precharge voltage.

5. The apparatus of claim 3 wherein the sense amplifier comprises a differential sense amplifier.

6. The apparatus of claim 1 wherein the estimating module causes the charge to flow in the bit line for variable time periods during the first, second and third modes of operation.

7. The apparatus of claim 6 wherein the first range of values is less than the second range of values.

8. The apparatus of claim 7 wherein the time period during the second mode of operation is shorter than the time period during the first mode of operation.

9. The apparatus of claim 7 wherein the time period during the third mode of operation is longer than the time period during the first mode of operation.

10. In a digital memory system including a memory cell arranged to store charge corresponding to first logical value when the quantity of stored charge lies within a first range of values and corresponding to a second logical value when the quantity of stored charge lies within a second range of values and also including a bit line coupled to the cell, a method of testing the integrity of the data represented by the charge comprising:

detecting during a first mode of operation whether the quantity of the charge lies within the first range of values or the second range of values;

detecting during a second mode of operation whether the quantity of the charge lies within a third range of values comprising a subset of the first range of values; and

detecting during a third mode of operation whether the quantity of the charge lies within a fourth range of values comprising a subset of the second range of values.

11. The method of claim 10 wherein the second mode of operation is entered only if the quantity of charge lies within the first range of values and wherein the third mode of operation is entered only if the quantity of the charge lies within the second range of values.

12. The method of claim 10 further comprising:

generating a bit line voltage in response to the charge stored in the memory cell;

generating a reference voltage;

generating a sense output voltage in response to the bit line voltage and the reference voltage;

placing a first load on the bit line during the second mode of operation; and

placing a second load on the bit line during the third mode of operation.

13. The method of claim 12 wherein said generating a reference voltage comprises precharging the bit line to generate a bit line precharge voltage and generating the reference voltage in response to the bit line precharge voltage.

14. The method of claim 12 wherein said generating a sense output voltage comprises generating a differential sense output voltage.

15. The method of claim 10 wherein said detecting during a first mode, detecting during a second mode and detecting during a third mode comprises:

generating a bit line voltage in response to the charge stored in the memory cell;

generating a reference voltage; and

comparing the bit line voltage and the reference voltage after variable time periods during the first, second and third modes of operation.

16. The method of claim 15 wherein the first range of values is less than the second range of values.

17. The method of claim 16 wherein time period during the second mode of operation is shorter than the time period during the first mode of operation.

18. The method of claim 16 wherein the time period during the third mode of operation is longer than the time period during the first mode of operation.