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Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory

  • US 6,754,106 B1
  • Filed: 09/16/2002
  • Issued: 06/22/2004
  • Est. Priority Date: 09/16/2002
  • Status: Active Grant
First Claim
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1. A load circuit comprising:

  • a select transistor of an mth load circuit in a plurality of load circuits; and

    m resistors coupled in series, said m resistors coupled to said mth load circuit, said mth load circuit for matching a source side loading effect of a corresponding mth memory cell located m memory cells away from a source line node on a source line coupling source regions in memory cells of a row of memory cells by reducing in series current contributions of a voltage associated with said source line node.

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