Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation

• US 6,754,111 B2
• Filed: 08/01/2003
• Issued: 06/22/2004
• Est. Priority Date: 02/11/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pekny, Theodore T.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/633,247
• Publication Number:
  US 20040027866A1
• Time in Patent Office: 326 Days
• Field of Search: 365/189.09, 365/194, 365/226, 365/229, 365/185.33
• US Class Current: 365/189.09
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A method of operating a memory includes generating a first reference voltage and detecting an active mode of operation of the memory. Upon detection of the active mode, commencing the charging of a node to develop a second reference voltage having a desired value on the node. The word line drive voltage is generated using the first reference voltage while the node is charging the second reference voltage to the desired value. The word line drive voltage is generated using the second reference voltage once the second reference voltage on the node has been charged to the desired value. A standby mode of operation of the memory is detected, and upon detection of the standby mode, the charging of the node is terminated and the word line drive voltage is generated using the first reference voltage.

Claims

1. A memory device, comprising:

an address bus;

a control bus;

a data bus;

an address decoder coupled to the address bus;

a read/write circuit coupled to the data bus;

a control circuit coupled to the control bus;

a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array including a plurality of word lines;

a voltage switching circuit, comprising,

an active voltage reference adapted to receive a mode signal, the active voltage reference operable responsive to the mode signal going active to generate a first reference voltage and operable responsive to the mode signal going inactive to terminate generation of the first reference voltage;

a standby voltage reference operable to generate a second reference voltage;

a charge pump operable to generate a row drive voltage having a value that is a function of a reference voltage;

a plurality of row drivers, each row driver being coupled to the address decoder to receive a corresponding decoded address signal and including an output coupled to a corresponding word line of the memory-cell array, and coupled to the charge pump to receive the row drive voltage, the row driver applying the row drive voltage on the word line responsive to the decoded address signal being active;

a multiplexer coupled to the active and standby voltage references to receive the first and second voltage references, respectively, and being coupled to the charge pump, the multiplexer applying the first reference voltage to the charge pump responsive to a selection signal going active, and applying the second reference voltage to the charge pump responsive to the selection signal going inactive;

a delay circuit coupled to the multiplexer and adapted to receive the mode signal, the delay circuit operable responsive to the mode signal going active to drive the selection signal active a delay time after the mode signal goes active, and operable responsive to the mode signal going inactive to drive the selection signal inactive without the delay time.

2. The memory device of claim 1 wherein the active and standby voltage references each comprise a bandgap voltage reference.

3. The memory device of claim 1 wherein the memory device comprises a flash memory.

4. The memory device of claim 1 wherein the mode signal comprises a chip enable signal applied on the control bus.

5. The memory device of claim 4 wherein the chip enable signal goes active to place the memory device in an active mode of operation and goes inactive to place the memory device in a standby mode of operation.

6. A computer system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and output devices; and

a memory device coupled to the processor, the memory device comprising,

an address bus;

a control bus;

a data bus;

an address decoder coupled to the address bus;

a read/write circuit coupled to the data bus;

a control circuit coupled to the control bus;

a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array including a plurality of word lines;

a voltage switching circuit, comprising,

an active voltage reference adapted to receive a mode signal, the active voltage reference operable responsive to the mode signal going active to generate a first reference voltage and operable responsive to the mode signal going inactive to terminate generation of the first reference voltage;

a standby voltage reference operable to generate a second reference voltage;

a charge pump operable to generate a row drive voltage having a value that is a function of a reference voltage;

a plurality of row drivers, each row driver being coupled to the address decoder to receive a corresponding decoded address signal and including an output coupled to a corresponding word line of the memory-cell array, and coupled to the charge pump to receive the row drive voltage, the row driver applying the row drive voltage on the word line responsive to the decoded address signal being active;

a multiplexer coupled to the active and standby voltage references to receive the first and second voltage references, respectively, and being coupled to the charge pump, the multiplexer applying the first reference voltage to the charge pump responsive to a selection signal going active, and applying the second reference voltage to the charge pump responsive to the selection signal going inactive;

a delay circuit coupled to the multiplexer and adapted to receive the mode signal, the delay circuit operable responsive to the mode signal going active to drive the selection signal active a delay time after the mode signal goes active, and operable responsive to the mode signal going inactive to drive the selection signal inactive without the delay time.

7. The computer system of claim 6 wherein the active and standby voltage references each comprise a bandgap voltage reference.

8. The computer system of claim 6 wherein the memory device comprises a flash memory.

9. The computer system of claim 6 wherein the mode signal comprises a chip enable signal applied on the control bus.

10. The computer system of claim 9 wherein the chip enable signal goes active to place the memory device in an active mode of operation and goes inactive to place the memory device in a standby mode of operation.

11. A method of operating a memory, the method comprising:

detecting an active mode of operation of the memory;

during the active mode of operation,

generating a first reference voltage;

generating a word line drive voltage using the first reference voltage;

receiving addresses corresponding to memory cells to be accessed; and

applying the word line drive voltage to the word line of addressed memory cells to access the memory cells in the corresponding row; and

detecting a standby mode of operation; and

during the standby mode of operation,

terminating generation of the first reference voltage;

generating a second reference voltage; and

generating the word line drive voltage using the second reference voltage.

12. The method of claim 11 wherein detecting the active and standby modes of operation comprises detecting a signal applied to the flash memory on the control bus.

13. The method of claim 12 wherein the signal comprises a chip enable signal.

14. The method of claim 11 wherein generating the first reference voltage consumes more power than generating the second reference voltage.

15. A method of operating a memory, the method comprising:

detecting an active mode of operation of the memory;

during the active mode of operation,

generating a first reference voltage that consumes a first amount of power in generating the first reference voltage;

generating a word line drive voltage using the first reference voltage;

generating a second reference voltage that consumes a second amount of power in generating the second reference voltage, the second amount of power being less than the first amount of power;

detecting a standby mode of operation of the memory; and

during the standby mode,

terminating generation of the first reference voltage; and

generating the word line drive voltage using the second reference voltage.

16. The method of claim 15 wherein detecting the active and standby modes of operation comprises detecting a signal applied to the flash memory on the control bus.

17. The method of claim 16 wherein the signal comprises a chip enable signal.

18. The method of claim 15 wherein the first reference voltage has a value that is more precise and stable relative to the value of the second reference voltage.

19. The method of claim 15 wherein generating a second reference voltage comprises generating the second reference voltage during the active and standby modes of operation.

20. A method of operating a memory, the method comprising:

detecting a standby mode of operation of the memory;

generating a first reference voltage;

generating a word line drive voltage using the first reference voltage;

detecting an active mode of operation of the memory;

during the active mode of operation,

generating a second reference voltage;

generating the word line drive voltage using the first reference voltage; and

generating the word line drive voltage using the second reference voltage.

21. The method of claim 20 wherein during the active mode the generation of the word line drive voltage using the first reference voltage comprises generating the word line drive voltage using the first reference voltage for a delay time, the delay time defining an interval after the detection of the active mode, and wherein during the active mode the generation of the word line drive voltage using the second reference voltage comprises generating the word line drive voltage using the second reference voltage after the delay time.

22. The method of claim 20 wherein during the active mode the generation of the word line drive voltage using the first reference voltage comprises generating the word line drive voltage using the first reference voltage for a predetermined number of data transfer operations after the start of the active mode, and wherein during the active mode the generation of the word line drive voltage using the second reference voltage comprises generating the word line drive voltage using the second reference voltage after the predetermined number of data transfer operations.

23. The method of claim 20 wherein detecting the active and standby modes of operation comprises detecting a signal applied to the flash memory on the control bus.

24. The method of claim 23 wherein the signal comprises a chip enable signal.

25. The method of claim 20 wherein the second reference voltage has a value that is more precise and stable relative to the value of the first reference voltage.

26. A method of operating a memory, the method comprising:

generating a first reference voltage;

detecting an active mode of operation of the memory;

upon detection of the active mode,

commencing the charging of a node to develop a second reference voltage on the node, the second reference voltage having desired value;

generating the word line drive voltage using the first reference voltage while the node is charging the second reference voltage to the desired value; and

generating the word line drive voltage using the second reference voltage once the second reference voltage on the node has been charged to the desired value;

detecting a standby mode of operation of the memory;

upon detection of the standby mode,

terminating the charging of the node; and

generating the word line drive voltage using the first reference voltage.

27. The method of claim 26 wherein generating the word line drive voltage using the first reference voltage while the node is charging the second reference voltage to the desired value comprises generating the word line drive voltage using the first reference voltage for a delay time, the delay time defining an interval after the active mode is detected, and wherein generating the word line drive voltage using the second reference voltage once the node has charged the second reference voltage to the desired value comprises generating the word line drive voltage using the second reference voltage after the delay time.

28. The method of claim 26 wherein generating the word line drive voltage using the first reference voltage while the node is charging the second reference voltage to the desired value comprises generating the word line drive voltage using the first reference voltage for a predetermined number of data transfer commands applied to the memory after the active mode is detected, and wherein generating the word line drive voltage using the second reference voltage once the node has charged the second reference voltage to the desired value comprises generating the word line drive voltage using the second reference voltage after the predetermined number of data transfer commands have been applied.

29. The method of claim 26 wherein detecting the active and standby modes of operation comprises detecting a signal applied to the flash memory on the control bus.

30. The method of claim 29 wherein the signal comprises a chip enable signal.

31. The method of claim 26 wherein the second reference voltage has a value that is more precise and stable relative to the value of the first reference voltage.