Transmitter and receiver for a very high speed digital subscriber line
First Claim
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1. A transmitter, wherein the transmitter is a Very High Speed Digital Subscriber Line (VDSL) transmitter comprising:
- a first input for receiving data (DATA);
a second input for receiving a network timing reference signal (CLK2);
a third input for receiving a transmitter sampling clock signal (CLK1);
an output for providing data frames (FRAME);
embedding circuitry (EMBED) coupled between said first input and said output, wherein the embedding circuitry is adapted to embed said data in said data frames (FRAME) and to output said data frames to said output; and
phase measurement circuitry (PHASE) coupled to said second input and responsive to a local timing reference signal (R), said local timing reference signal (R) being derived from said transmitter sampling clock signal (CLK1), wherein said phase measurement circuitry (PHASE) is adapted to measure a phase offset value (P) between said network timing reference signal (CLK2) and said local timing reference signal (R), and to output said phase offset value (P) to said embedding circuitry (EMBED);
wherein said embedding circuitry (EMBED) is further conFIGUREd so as to embed in one of said data frames (FRAME) a change of said phase offset value (P) from a previously measured phase offset value (P).
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Abstract
To transparently transport an incoming clock signal (CLK2) with a known frequency over a network segment wherein transmission between a transmitter (TX) and a receiver (RX) operates synchronous to a transmit clock signal (CLK1) and receiver clock signal (CLK1′) which are synchronized, the transmitter measures the phase difference (P) between the incoming clock signal (CLK2) and a reference signal (R) obtained from the transmit clock signal (CLK1). The measured phase difference (P) is communicated to the receiver (RX) and used therein to generate a copy (CLK2)
71 Citations
10 Claims
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1. A transmitter, wherein the transmitter is a Very High Speed Digital Subscriber Line (VDSL) transmitter comprising:
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a first input for receiving data (DATA);
a second input for receiving a network timing reference signal (CLK2);
a third input for receiving a transmitter sampling clock signal (CLK1);
an output for providing data frames (FRAME);
embedding circuitry (EMBED) coupled between said first input and said output, wherein the embedding circuitry is adapted to embed said data in said data frames (FRAME) and to output said data frames to said output; and
phase measurement circuitry (PHASE) coupled to said second input and responsive to a local timing reference signal (R), said local timing reference signal (R) being derived from said transmitter sampling clock signal (CLK1), wherein said phase measurement circuitry (PHASE) is adapted to measure a phase offset value (P) between said network timing reference signal (CLK2) and said local timing reference signal (R), and to output said phase offset value (P) to said embedding circuitry (EMBED);
wherein said embedding circuitry (EMBED) is further conFIGUREd so as to embed in one of said data frames (FRAME) a change of said phase offset value (P) from a previously measured phase offset value (P). - View Dependent Claims (2, 3, 4, 5)
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6. A receiver, wherein the receiver is a Very High Speed Digital Subscriber Line (VDSL) comprising:
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a receiver input for receiving data frames (FRAME);
a clock input for receiving a receiver sampling clock signal (CLK1′
);
a first receiver output for providing a received output signal (DATA′
) and a second receiver output for providing a clock output (CLK2′
);
retrieving circuitry (D-EMBED) adapted to retrieve incoming data (DATA′
) from said data frames (FRAME), to output said retrieved data (DATA′
) to said first receiver output, and to retrieve a change of a phase offset value (P) from a previously recovered phase offset value (P) out of a reserved field within said data frames (FRAME);
local timing reference signal circuitry adapted to generate a local timing reference signal (R′
) from said receiver sampling clock signal (CLK1′
); and
a clock generator (GEN) having a first input for receiving said change of said phase offset value (P), and a second input for receiving said local timing reference signal (R′
), wherein said clock generator (GEN) is conFIGUREd so as to generate a clock signal (CLK2′
) having a phase offset from said local timing reference signal (R′
) generally equal to said phase offset value (P).- View Dependent Claims (7, 8, 9, 10)
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Specification
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Current AssigneeRPX Corporation
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Original AssigneeNokia Corporation
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InventorsSpruyt, Paul Marie Pierre, Van Der Putten, Frank Octaaf
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Primary Examiner(s)Kizou, Hassan
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Assistant Examiner(s)Elallam, Ahmed
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Application NumberUS09/906,531Publication NumberTime in Patent Office1,072 DaysField of Search370/503, 370/507, 370/508, 370/516, 370/518, 370/527, 370/528, 375/106, 375/108, 375/356, 375/371, 375/377US Class Current370/503CPC Class CodesH04J 3/0638 Clock or time synchronisati...
